Which table for a dynamic pipeline become more interesting when a nonlinear pattern is follows?
Reservation Table
A pipeline's use of its stages over time is described by a reservation table: rows are the stages, columns are clock cycles, and a mark shows which stage is busy in which cycle while one task passes through.
For a linear (static) pipeline the reservation table is a simple diagonal, because each task flows through the stages once in order, so the table carries little information. In a dynamic, nonlinear pipeline with feed-forward and feedback connections, a task can revisit a stage, so the marks form an irregular pattern. That pattern determines the forbidden latencies, the collision vector and the state diagram used to schedule new initiations, which is why the reservation table becomes much more interesting for nonlinear patterns.
A confusion table (confusion matrix) belongs to classifier evaluation, an inverted table is a file or page-table organisation, and a greedy table is not a pipeline structure; greedy cycles are derived from the reservation table's state diagram, not stored as a table of their own.
Reservation Table option is correct.
Similar Questions
In the case of parallelization, Amdahl’s law states that if P is the proportion of a program that can be made parallel and \((1-P)\) is the proportion that cannot be parallelized, then the maximum speed-up that can be achieved by using N processors is :
A vector processor with 16 lanes can perform an operation on 1024 elements with each operation taking 5 clock cycles. How many cycles are needed to complete the operation ?
A CPU has a 5-stage pipeline with the following stages Fetch (F), Decode (D), Execute (E), Memory (M) and Write-back (W). Each stage takes one clock cycle to complete. Assume there are no pipeline stalls and the pipeline is initially empty. How many clock cycles are required to complete the execution of 10 instructions ?
A multi processor system with 16 processors is used to execute a parallelizable task. If the serial portion of the task takes 200 clock cycles and the parallel portion take 800 clock cycles. When all 16 processor are used how many total clock cycles are required to complete the task ?
Important Questions from Instruction Pipeline
Which one of the following is false about Pipelining?
In the case of parallelization, Amdahl’s law states that if P is the proportion of a program that can be made parallel and \((1-P)\) is the proportion that cannot be parallelized, then the maximum speed-up that can be achieved by using N processors is :
A vector processor with 16 lanes can perform an operation on 1024 elements with each operation taking 5 clock cycles. How many cycles are needed to complete the operation ?
A CPU has a 5-stage pipeline with the following stages Fetch (F), Decode (D), Execute (E), Memory (M) and Write-back (W). Each stage takes one clock cycle to complete. Assume there are no pipeline stalls and the pipeline is initially empty. How many clock cycles are required to complete the execution of 10 instructions ?
A multi processor system with 16 processors is used to execute a parallelizable task. If the serial portion of the task takes 200 clock cycles and the parallel portion take 800 clock cycles. When all 16 processor are used how many total clock cycles are required to complete the task ?
