A vector processor with 16 lanes can perform an operation on 1024 elements with each operation taking 5 clock cycles. How many cycles are needed to complete the operation ?
64
A vector processor splits a long vector into groups that are processed in parallel by its lanes. Each lane is a pipelined functional unit: although one operation takes several cycles from start to finish, a new element can enter the lane every cycle, so in steady state each lane delivers one result per cycle and the operation latency is overlapped.
Step 1 — With 16 lanes, 16 elements are handled in each cycle.
Step 2 — Number of element groups: \(\dfrac{1024}{16} = 64\).
Step 3 — Since one group is issued per cycle and the 5-cycle latency of each operation is hidden by pipelining inside the lanes, the vector operation is counted as 64 cycles.
A count of 80 cycles would match neither the lane count nor the latency, 100 has no relation to 1024 elements over 16 lanes, and 128 would correspond to only 8 lanes processing the vector.
64 option is correct.
Similar Questions
In the case of parallelization, Amdahl’s law states that if P is the proportion of a program that can be made parallel and \((1-P)\) is the proportion that cannot be parallelized, then the maximum speed-up that can be achieved by using N processors is :
Which table for a dynamic pipeline become more interesting when a nonlinear pattern is follows?
A CPU has a 5-stage pipeline with the following stages Fetch (F), Decode (D), Execute (E), Memory (M) and Write-back (W). Each stage takes one clock cycle to complete. Assume there are no pipeline stalls and the pipeline is initially empty. How many clock cycles are required to complete the execution of 10 instructions ?
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Important Questions from Instruction Pipeline
Which one of the following is false about Pipelining?
In the case of parallelization, Amdahl’s law states that if P is the proportion of a program that can be made parallel and \((1-P)\) is the proportion that cannot be parallelized, then the maximum speed-up that can be achieved by using N processors is :
Which table for a dynamic pipeline become more interesting when a nonlinear pattern is follows?
A CPU has a 5-stage pipeline with the following stages Fetch (F), Decode (D), Execute (E), Memory (M) and Write-back (W). Each stage takes one clock cycle to complete. Assume there are no pipeline stalls and the pipeline is initially empty. How many clock cycles are required to complete the execution of 10 instructions ?
A multi processor system with 16 processors is used to execute a parallelizable task. If the serial portion of the task takes 200 clock cycles and the parallel portion take 800 clock cycles. When all 16 processor are used how many total clock cycles are required to complete the task ?
