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Question

In the case of parallelization, Amdahl’s law states that if P is the proportion of a program that can be made parallel and \((1-P)\) is the proportion that cannot be parallelized, then the maximum speed-up that can be achieved by using N processors is :

This question was previously asked in
UGC NET 2015 Paper 1 Question Paper (27-Dec-2015)
The correct answer is

\(\frac{1}{(1-P)+\frac{P}{N}}\)

Take the serial running time as 1; the part \(1-P\) cannot be sped up, while the part P is shared across N processors.

New time \(= (1-P) + \frac{P}{N}\)

Speed-up \(= \frac{1}{(1-P) + \frac{P}{N}}\)

Check: with \(P = 1\) the speed-up is N, and with \(P = 0\) it is 1, as expected.

Hence, \(\frac{1}{(1-P)+\frac{P}{N}}\).

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Similar Questions

  1. Which table for a dynamic pipeline become more interesting when a nonlinear pattern is follows?

  2. A vector processor with 16 lanes can perform an operation on 1024 elements with each operation taking 5 clock cycles. How many cycles are needed to complete the operation ?

  3. A CPU has a 5-stage pipeline with the following stages Fetch (F), Decode (D), Execute (E), Memory (M) and Write-back (W). Each stage takes one clock cycle to complete. Assume there are no pipeline stalls and the pipeline is initially empty. How many clock cycles are required to complete the execution of 10 instructions ?

  4. A multi processor system with 16 processors is used to execute a parallelizable task. If the serial portion of the task takes 200 clock cycles and the parallel portion take 800 clock cycles. When all 16 processor are used how many total clock cycles are required to complete the task ?


Important Questions from Instruction Pipeline

  1. Which one of the following is false about Pipelining?

  2. Which table for a dynamic pipeline become more interesting when a nonlinear pattern is follows?

  3. A vector processor with 16 lanes can perform an operation on 1024 elements with each operation taking 5 clock cycles. How many cycles are needed to complete the operation ?

  4. A CPU has a 5-stage pipeline with the following stages Fetch (F), Decode (D), Execute (E), Memory (M) and Write-back (W). Each stage takes one clock cycle to complete. Assume there are no pipeline stalls and the pipeline is initially empty. How many clock cycles are required to complete the execution of 10 instructions ?

  5. A multi processor system with 16 processors is used to execute a parallelizable task. If the serial portion of the task takes 200 clock cycles and the parallel portion take 800 clock cycles. When all 16 processor are used how many total clock cycles are required to complete the task ?

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