All Exams Test series for 1 year @ ₹349 only
Question

A multi processor system with 16 processors is used to execute a parallelizable task. If the serial portion of the task takes 200 clock cycles and the parallel portion take 800 clock cycles. When all 16 processor are used how many total clock cycles are required to complete the task ?

This question was previously asked in
UGC NET 2024 Management Question Paper (02-Sep-2024) (Shift 2)
The correct answer is

250

Amdahl's law models a task as a serial part, which only one processor can execute, and a parallel part, which can be divided equally among all processors. The total time with N processors is the serial time plus the parallel time divided by N.

Step 1 — Serial portion: 200 clock cycles, unchanged by the number of processors.

Step 2 — Parallel portion on 16 processors: \(\dfrac{800}{16} = 50\) clock cycles.

Step 3 — Total: \(200 + 50 = 250\) clock cycles. (On a single processor the task would take 1000 cycles, so the speedup is 4.)

A total of 300 would mean the parallel part ran on only 8 processors, 400 would mean only 4 processors, and 450 does not match an equal split of 800 cycles across the 16 processors.

250 option is correct.

Was this answer helpful?

Similar Questions

  1. In the case of parallelization, Amdahl’s law states that if P is the proportion of a program that can be made parallel and \((1-P)\) is the proportion that cannot be parallelized, then the maximum speed-up that can be achieved by using N processors is :

  2. Which table for a dynamic pipeline become more interesting when a nonlinear pattern is follows?

  3. A vector processor with 16 lanes can perform an operation on 1024 elements with each operation taking 5 clock cycles. How many cycles are needed to complete the operation ?

  4. A CPU has a 5-stage pipeline with the following stages Fetch (F), Decode (D), Execute (E), Memory (M) and Write-back (W). Each stage takes one clock cycle to complete. Assume there are no pipeline stalls and the pipeline is initially empty. How many clock cycles are required to complete the execution of 10 instructions ?


Important Questions from Instruction Pipeline

  1. Which one of the following is false about Pipelining?

  2. In the case of parallelization, Amdahl’s law states that if P is the proportion of a program that can be made parallel and \((1-P)\) is the proportion that cannot be parallelized, then the maximum speed-up that can be achieved by using N processors is :

  3. Which table for a dynamic pipeline become more interesting when a nonlinear pattern is follows?

  4. A vector processor with 16 lanes can perform an operation on 1024 elements with each operation taking 5 clock cycles. How many cycles are needed to complete the operation ?

  5. A CPU has a 5-stage pipeline with the following stages Fetch (F), Decode (D), Execute (E), Memory (M) and Write-back (W). Each stage takes one clock cycle to complete. Assume there are no pipeline stalls and the pipeline is initially empty. How many clock cycles are required to complete the execution of 10 instructions ?

Need Expert Advice?
Upcoming Exams
CTET
December 12, 2026
CBSE UGC NET
December 14, 2026
CSIR UGC NET
December 19, 2026
Test Series
UGC NET img
Teaching
UGC NET (Paper 2) 2026 Mock Test Series
796 Tests 2 Tests Free
4.4(40)
English
More Questions from UGC NET

Start Your Preparation with Prepp Mobile App

Download the app from Google Play & App Store
Download the app from Google Play & App Store
Prepp Mobile App