When exposed to light, the positive resists in developer solution responds by becoming :
more soluble
The word "positive" carries the answer: a positive resist becomes more soluble where light strikes it, so the exposed pattern washes away in the developer — option 4.
| Positive resist | Negative resist | |
|---|---|---|
| Effect of light | Bonds broken — becomes soluble | Cross-linked — becomes insoluble |
| What the developer removes | The exposed regions | The unexposed regions |
| Pattern on the wafer | Same as the mask | Reverse of the mask |
| Resolution | Better | Poorer — swells in developer |
The chemistry behind it. A common positive resist is a novolac resin mixed with a diazonaphthoquinone sensitiser. Unexposed, the sensitiser acts as a dissolution inhibitor and the film resists the alkaline developer. Ultraviolet light converts it through a Wolff rearrangement into an indene carboxylic acid, which is readily attacked by the alkaline developer — so the exposed film dissolves perhaps a hundred times faster than the unexposed film. The light does not simply weaken the resist; it changes the chemistry from inhibitor to accelerator.
Negative resists work the opposite way. There the incident photons initiate cross-linking, tying the polymer chains into a network that the developer cannot dissolve, so the unexposed regions are removed instead.
Why positive resist dominates in modern fabrication. A negative resist absorbs developer and swells as it is cross-linked, distorting the pattern and limiting resolution to a micrometre or so. Positive resist dissolves cleanly without swelling, giving the near-vertical sidewalls and sub-micron features that integrated-circuit lithography demands. That is also why option 3, "partially soluble", is not the answer — a partial change would give ragged, poorly defined edges, whereas the whole value of the process lies in the large contrast between exposed and unexposed dissolution rates.
Where it sits in the process : spin the resist, soft bake, expose through the mask, develop, hard bake, etch the layer beneath, then strip the remaining resist — a cycle repeated for each of the dozen or more masks in a CMOS flow.
Hence, a positive resist exposed to light becomes more soluble.
To form the integrated circuits, VLSI technology uses
The application of SiO2 in VLSI technology is mainly
A. to use it as a 'Mask'.
B. to provide electrical isolation.
C. to provide surface activation.
D. to provide electrical conduction.
E. as a etching material.
Choose the most appropriate answer from the options given below :
Match List I with List II
| LIST I ( IC classification) | LIST II (Number of transistors used) |
| A. VLSI | I. 1000 \(\lt\) Number of transistors \(\lt\) 10,000 |
| B. MSI | II. Number of transistors \(\gt\) 10,000 |
| C. LSI | III. Number of transistors \(\lt\) 100 |
| D. SSI | IV. 100 \(\lt\) Number of transistors \(\lt\) 1,000 |
Choose the correct answer from the options given below:
In VLSI Design flow,
A. Algorithm describes the behaviour of target chip.
B. Architecture of processor is not mapped onto the chip surface by floor planning.
C. Behavioral domain defines FSMs.
D. Individual modules are implemented with leaf cells.
Choose the correct answer from the options given below:
The correct design flow of VLSI is :
A. Functional Design & verification
B. Circuit Design & verification
C. Logic Design & verification
D. Physical Design
E. Layout verification
Choose the correct answer from the options given below :
Assertion (A) : E-beam lithography is used for drawing nanostructures.
Reason (R) : E-beam lithography has high resolution than photo lithography.
Select your answer using the codes given below :
Microprocessor development had happened because of LSI. What is LSI ?
To form the integrated circuits, VLSI technology uses
The application of SiO2 in VLSI technology is mainly
A. to use it as a 'Mask'.
B. to provide electrical isolation.
C. to provide surface activation.
D. to provide electrical conduction.
E. as a etching material.
Choose the most appropriate answer from the options given below :
Match List I with List II
| LIST I ( IC classification) | LIST II (Number of transistors used) |
| A. VLSI | I. 1000 \(\lt\) Number of transistors \(\lt\) 10,000 |
| B. MSI | II. Number of transistors \(\gt\) 10,000 |
| C. LSI | III. Number of transistors \(\lt\) 100 |
| D. SSI | IV. 100 \(\lt\) Number of transistors \(\lt\) 1,000 |
Choose the correct answer from the options given below:
In VLSI Design flow,
A. Algorithm describes the behaviour of target chip.
B. Architecture of processor is not mapped onto the chip surface by floor planning.
C. Behavioral domain defines FSMs.
D. Individual modules are implemented with leaf cells.
Choose the correct answer from the options given below: