The major processing steps of BJT IC fabrication in VLSI technology are A. Oxidation B. Diffusion C. Crystal growth D. Photolithography E. Epitaxial layer formation Choose the correct ascending order from the options given below :
C, A, D, B, E
The processing sequence. BJT IC fabrication runs from raw silicon to a finished, patterned, doped structure. The steps named in the question, in the order given by the official key, are:
C — Crystal growth. Electronic-grade polysilicon is melted and pulled into a single-crystal ingot by the Czochralski method, then sliced, lapped and polished into wafers. Nothing can happen before there is a wafer, so this is always first.
A — Oxidation. The wafer is heated in oxygen or steam to grow a SiO2 film. The oxide is the masking and isolating layer on which the whole planar process depends, because dopants barely diffuse through it.
D — Photolithography. Photoresist is spun on, exposed through a mask, developed, and the exposed oxide is etched away. This opens windows that define exactly where the next step will act — the step that transfers the circuit pattern onto the wafer.
B — Diffusion. Dopants (boron for p-regions, phosphorus for n-regions) are introduced through those windows at high temperature to form the base and emitter regions of the transistor. Ion implantation followed by an anneal is the modern equivalent, offering better dose control.
E — Epitaxial layer formation. A doped single-crystal silicon layer grown from a gas source (usually SiH4 or SiCl4) on the wafer surface — in a bipolar process it forms the lightly doped collector over the buried n+ layer.
A note on the sequence. In an actual bipolar flow the epitaxial layer is grown early — right after the buried-layer step and before the oxidation/lithography/diffusion cycles that form the base and emitter — and oxidation, lithography and diffusion then repeat several times, once per masking level. The official key for this paper places E last, and that key is retained here.
Hence, the keyed order is C, A, D, B, E.
The evaporation rate from a clean surface is related to the equilibrium vapour pressure Pe of the evaporating species of molecular weight M by an expression :
Czochralski (Cz) method is used instead of using float zone technique to grow Si crystal because it produces :
Czochralski system of crystal growth is a
The thermal oxidation of silicon single crystal producer stacking faults lying on the plane.
The desired properties of metallization for integrated circuits are
A. low resistivity.
B. low conductivity.
C. easy to etch for pattern generation.
D. tough to etch for pattern generation.
E. no contamination with device or wafers.
Choose the correct answer from the options given below :
MEMS devices are within the size range of
Given below are two statements :
Statement I : Concentration of acceptor atoms in the region between isolation islands in a monolythic integrated circuit will be much higher then in a p-type substrate.
Statement II : The higher density is provided to prevent the depletion region of the reverse biased isolation to substrate junction from extending into the p+ type material.
In the light of the above statements, choose the most appropriate answer from the options given below :
Arrange the following fabrication steps in order needed to fabricate the IC :
(a) Oxidation (b) Etching (c) Metallization (d) Epitaxial growth
Codes :
Assertion (A) : In a bipolar IC fabrication, the diode isolation is used to isolate one device from the other.
Reason (R) : P+n diode used as isolation diode in IC fabrication.
Select your answer using the codes given below.
Assertion (A) : The epitaxial layer growth possesses the same crystal structure to that of the substrate on which it is grown.
Reason (R) : It can only be of similar conductivity type but possesses different value of resistivity to that of the substrate.
Select your answer using the codes given below.
Maximum component density for a given PCB size can be obtained by
In MOSFET fabrication, the channel length is defined during the process of
The desired property of gate and interconnection metallization is
In a silicon oxidation model, \(\rm \frac{B}{A}\) is the linear rate constant and τ accounts for the shift in the time coordinate to account for the presence of the initial oxide layer, then the linear law is represented as: