Match the following : Codes : List - I List - II (a) Minimization (i) Multiplexer (b) Successive Approximation (ii) Shift Register (c) Data Selector (iii) A/D Convertor (d) Sequence Generator (iv) QM Metdod
(a)-(iv), (b)-(iii), (c)-(i), (d)-(ii)
All four links are one-to-one and unambiguous.
(a) Minimization → (iv) QM method. The Quine-McCluskey method is the tabular algorithm for simplifying Boolean functions. Unlike the Karnaugh map, which relies on visual grouping and becomes impractical beyond five or six variables, QM is systematic: it repeatedly combines terms differing in exactly one bit to build prime implicants, then uses a prime-implicant chart to pick a minimal cover. Being algorithmic, it is what a computer actually runs, and it is the reason the method still matters despite being tedious by hand.
(b) Successive approximation → (iii) A/D converter. The SAR ADC is the standard medium-speed converter. It performs a binary search: the MSB of the SAR is set, the DAC output is compared with the input, the bit is kept or cleared, and the process repeats down to the LSB. An n-bit conversion therefore takes exactly n clock cycles, regardless of the input value — a fixed and predictable latency, which is precisely why SAR converters dominate data-acquisition front ends.
(c) Data selector → (i) multiplexer. "Data selector" is simply the functional name for a multiplexer. With n select lines it routes one of \(2^{n}\) inputs to the single output:
\(Y=\sum_{i=0}^{2^{n}-1} m_{i}\,I_{i}\)
Because that expression is a full sum of minterms, a MUX can also implement any Boolean function of its select variables directly — the classic "MUX as universal logic element" trick.
(d) Sequence generator → (ii) shift register. A shift register with feedback from selected stages (the linear-feedback shift register) cycles through a fixed sequence of states, generating pseudo-random or prescribed bit patterns. An n-stage LFSR with a primitive feedback polynomial produces a maximal-length sequence of \(2^{n}-1\) states, used in test-pattern generation, scramblers and spread-spectrum codes.
| List-I | Belongs to | Code |
|---|---|---|
| Minimization | Quine-McCluskey | (iv) |
| Successive approximation | ADC | (iii) |
| Data selector | Multiplexer | (i) |
| Sequence generator | Shift register | (ii) |
The order (iv), (iii), (i), (ii) is option 2.
Hence, the correct match is (a)-(iv), (b)-(iii), (c)-(i), (d)-(ii).
Similar Questions
Assertion (A) : A demultiplexer can be used as a decoder.
Reason (R) : A demultiplexer is built by using AND gates only.
Match the following :
List – I List – II a. Shift Register i. Frequency Division b. Multiplexer ii. Memory chip select generation c. Decoder iii. Parallel to serial conversion d. Counter iv. Many to one switch Codes :
List – I List – II a. Multiplexer i. Selects one of many inputs to a single output b. Flip-Flop ii. Combinational circuit c. Shift Register iii. Memory d. Parallel Adder iv. Sequential logic Codes :
Assertion (A) : A decoder is dissimilar to a demultiplexer.
Reason (R) : There is no data input in a decoder.
Select your answer using the codes given below.
Important Questions from Combinational Circuits
Which of the following represents the borrow in a half subtraction?
Carry input is present in which of the following?
The number of control lines for 8-to-1 multiplexer is:
X/Y (where X represents the input code and Y represents the output code) as a qualifying symbol does NOT relate to:
Consider 4-bit gray code representation of numbers. Let h3 h2 h1 h0 be the gray code representation of a number n and g1g2g3g0 be the gray code representation of the number (n + 1) modulo 16. Which one of the following functions is correct?
