Codes :List – I List – II a. Multiplexer i. Selects one of many inputs to a single output b. Flip-Flop ii. Combinational circuit c. Shift Register iii. Memory d. Parallel Adder iv. Sequential logic
a-i, b-iii, c-iv, d-ii
Every option pairs the multiplexer with (i), so the question really turns on the other three.
(a) Multiplexer → (i) selects one of many inputs to a single output. That is the definition — a data selector. With n select lines it routes one of \(2^{n}\) inputs through, according to
\(Y=\sum_{i=0}^{2^{n}-1}m_{i}I_{i}\)
(b) Flip-flop → (iii) memory. A flip-flop is the elementary one-bit store: it holds its state indefinitely until clocked, which is precisely what memory means. Every register, counter and RAM cell is built from them.
(c) Shift register → (iv) sequential logic. Its output depends not only on the present input but on what was clocked in previously — the defining property of a sequential circuit. It is made of flip-flops in a chain, each feeding the next.
(d) Parallel adder → (ii) combinational circuit. The sum depends only on the bits presently applied; there is no clock and no stored state. Give it the same inputs and it always gives the same output.
The order (i), (iii), (iv), (ii) is option 1.
| Combinational | Sequential | |
|---|---|---|
| Output depends on | Present inputs only | Present inputs and past history |
| Memory element | None | Flip-flops |
| Clock | Not required | Usually required |
| Examples | Adder, MUX, decoder, encoder, comparator | Flip-flop, register, counter, state machine |
The distinction is the organising principle of the whole subject, and the multiplexer illustrates it neatly: although it is combinational, a MUX with its output fed back to one input becomes a storage element — which is exactly how a D flip-flop with an enable is built. The line between the two families is feedback.
A note on the parallel adder : the ripple-carry version is combinational but slow, since the carry must propagate through all n stages, giving a delay proportional to n. The carry-look-ahead adder computes every carry directly from the inputs, reducing the delay to a constant at the cost of more gates — still entirely combinational.
Hence, the correct match is a-i, b-iii, c-iv, d-ii.
Similar Questions
Assertion (A) : A demultiplexer can be used as a decoder.
Reason (R) : A demultiplexer is built by using AND gates only.
Match the following :
List – I List – II a. Shift Register i. Frequency Division b. Multiplexer ii. Memory chip select generation c. Decoder iii. Parallel to serial conversion d. Counter iv. Many to one switch Codes :
Match the following :
List - I List - II (a) Minimization (i) Multiplexer (b) Successive Approximation (ii) Shift Register (c) Data Selector (iii) A/D Convertor (d) Sequence Generator (iv) QM Metdod Codes :
Assertion (A) : A decoder is dissimilar to a demultiplexer.
Reason (R) : There is no data input in a decoder.
Select your answer using the codes given below.
Important Questions from Combinational Circuits
Which of the following represents the borrow in a half subtraction?
Carry input is present in which of the following?
The number of control lines for 8-to-1 multiplexer is:
X/Y (where X represents the input code and Y represents the output code) as a qualifying symbol does NOT relate to:
Consider 4-bit gray code representation of numbers. Let h3 h2 h1 h0 be the gray code representation of a number n and g1g2g3g0 be the gray code representation of the number (n + 1) modulo 16. Which one of the following functions is correct?
