List - I
(Load impedance)List - II
(Value of reflection coefficient)A. Short circuit I. $0$ B. Open circuit II. $-1$ C. Line characteristic impedance III. $+1$ D. 2 times of line characteristic impedance IV. $+\frac{1}{3}$
The reflection coefficient ($\Gamma$) at a load ($Z_L$) in a transmission line with characteristic impedance ($Z_0$) is given by the formula:
$ \Gamma = \frac{Z_L - Z_0}{Z_L + Z_0} $
We need to match the load impedance types in List-I with their corresponding reflection coefficient values in List-II.
For a short circuit, the load impedance is zero, i.e., $Z_L = 0$.
Calculating the reflection coefficient:
$ \Gamma = \frac{0 - Z_0}{0 + Z_0} = \frac{-Z_0}{Z_0} = -1 $
So, Short circuit matches with value -1 (List-II: II).
For an open circuit, the load impedance is infinite, i.e., $Z_L = \infty$.
To calculate $\Gamma$ when $Z_L = \infty$, we consider the limit:
$ \Gamma = \lim_{Z_L \to \infty} \frac{Z_L - Z_0}{Z_L + Z_0} = \lim_{Z_L \to \infty} \frac{1 - Z_0/Z_L}{1 + Z_0/Z_L} = \frac{1 - 0}{1 + 0} = 1 $
So, Open circuit matches with value +1 (List-II: III).
When the load impedance equals the line characteristic impedance, $Z_L = Z_0$.
Calculating the reflection coefficient:
$ \Gamma = \frac{Z_0 - Z_0}{Z_0 + Z_0} = \frac{0}{2Z_0} = 0 $
So, Line characteristic impedance matches with value 0 (List-II: I).
Here, the load impedance is $Z_L = 2Z_0$.
Calculating the reflection coefficient:
$ \Gamma = \frac{2Z_0 - Z_0}{2Z_0 + Z_0} = \frac{Z_0}{3Z_0} = \frac{1}{3} $
So, 2 times line characteristic impedance matches with value +1/3 (List-II: IV).
Based on the calculations:
The correct matching is A-II, B-III, C-I, D-IV.
| List - I (Addressing Modes) | List - II (Instruction) |
| A. Immediate Addressing | I. LDAX B |
| B. Register Addressing | II. OUT 01H |
| C. Direct Addressing | III. MVI B, 37H |
| D. Indirect Addressing | IV. MOV A, B |
| List - I | List - II |
| (Memory) | (Characteristic) |
| A. ROM | I. Volatile, Fast, Expensive |
| B. EPROM | II. UV erasable |
| C. EEPROM | III. Electrically erasable |
| D. SRAM | IV. Non-Volatile, permanent data |
| List - I | List - II |
| (Bus/Logic) | (Function/Characteristic) |
| A. Address bus | I. Carries read/write signals, timing signals, and interrupt signals |
| B. Data bus | II. A three-state output that can be high, low, or high-impedance |
| C. Control bus | III. Unidirectional lines used by CPU to point to a memory location or I/O device |
| D. Tristate logic | IV. Bidirectional lines used for transferring data between the CPU and memory |