For the n-channel MOSFET shown in the figure given below, threshold voltage Vth = 2 V. The drain current ID of the MOSFET is 4 mA when the drain resistance RD is 1 kΩ. If the value of RD is increased to 4 kΩ, then the drain current ID will become :
1.4 mA
Read the connection first — it is what makes the problem solvable. The gate is tied to the drain, so
\(V_{GS}=V_{DS}\)
A diode-connected MOSFET is always in saturation, because \(V_{DS}=V_{GS} \gt V_{GS}-V_{th}\) is satisfied automatically. So the square law applies throughout:
\(I_D=K\left(V_{GS}-V_{th}\right)^{2}\)
Step 1 — use the first condition to find K. With RD = 1 kΩ and ID = 4 mA, the drain (and hence the gate) sits at
\(V_{GS}=V_{DS}=10-(4\ \text{mA})(1\ \text{k}\Omega)=10-4=6\ \text{V}\)
\(K=\dfrac{I_D}{(V_{GS}-V_{th})^{2}}=\dfrac{4}{(6-2)^{2}}=\dfrac{4}{16}=0.25\ \text{mA/V}^{2}\)
Step 2 — write the load line for the new resistor. With RD = 4 kΩ and ID in mA,
\(V_{GS}=10-4I_D\)
Step 3 — solve the two together.
\(I_D=0.25\left(10-4I_D-2\right)^{2}=0.25\left(8-4I_D\right)^{2}=4\left(2-I_D\right)^{2}\)
\(I_D=4\left(4-4I_D+I_D^{2}\right)\)
\(4I_D^{2}-17I_D+16=0\)
\(I_D=\dfrac{17\pm\sqrt{289-256}}{8}=\dfrac{17\pm5.745}{8}\)
giving \(I_D=2.84\ \text{mA}\) or \(I_D=1.41\ \text{mA}\).
Step 4 — reject the spurious root. A quadratic from a square law always returns two roots and only one is physical. Test each against \(V_{GS} \gt V_{th}\):
| Root | VGS = 10 − 4ID | Valid? |
|---|---|---|
| 2.84 mA | −1.37 V | Below Vth — the device would be off, contradiction ✗ |
| 1.41 mA | 4.37 V | Above the 2 V threshold ✓ |
So \(I_D\approx1.4\ \text{mA}\) — option 3.
The sanity check. Raising RD from 1 kΩ to 4 kΩ must reduce the current, since the load line becomes steeper and intersects the square-law curve lower down. The current falls from 4 mA to 1.4 mA ✓. Note that it does not fall by the full factor of four, because as the current drops the drain voltage rises, which raises VGS and partly compensates — the self-limiting behaviour of the diode connection.
Why this configuration matters. A diode-connected MOSFET behaves as a non-linear two-terminal resistor and is the standard active load and current-mirror input device in analogue CMOS, precisely because its operating point is set by the current rather than by a fragile bias voltage.
Hence, the drain current becomes 1.4 mA.
In enhancement mode MOSFET the saturation (drain) current is given by
(a) \(K\dfrac{W}{L}(V_{gs}-V_{th})^{2}\)
(b) \(K\dfrac{W}{L}(V_{gs}-V_{th})(1+\lambda V_{ds})\)
(c) \(K\dfrac{W}{L}(V_{gs}-V_{th})^{2}(1+\lambda V_{ds})\)
(d) \(K\dfrac{W}{L}(V_{gs}-V_{th})^{2}(1-\lambda V_{ds})\)
Out of these
For an n-channel MOS transistor with $\mu_n$ = 600 cm2/Vs, Cox = 7 x 10-8 F/cm2, W = 40 $\mu_m$, L = 4$\mu_m$ and VTO=1.0 V, the value of K parameter is:
Approximate oxide capacitance value (Cgd) for saturation operating mode of MOS transistor is:
In MOS
A. The substrate fermi potential ϕF is negative in NMOS
B. The substrate fermi potential ϕF is positive in NMOS
C. The substrate bias voltage VSB is positive in NMOS, negative in PMOS
D. The substrate bias voltage VSB is negative in NMOS, positive in PMOS.
Choose the correct answer from the options given below:
In a MOSFET the drain saturation current is
The threshold voltage of a MOSFET can be lowered by
1. using a thinner gate oxide
2. reducing the carrier concentration in the substrate
3. increasing the carrier concentration in the substrate
Of these statements :
The threshold voltage of an n-channel MOSFET can be increased by
The threshold voltage of an n-channel MOSFET can be increased by
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Reason (R) : MOS ICs have small size and are easy to fabricate.
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