For the n-channel MOSFET shown in the figure given below, threshold voltage Vth = 2 V. The drain current ID of the MOSFET is 4 mA when the drain resistance RD is 1 kΩ. If the value of RD is increased to 4 kΩ, then the drain current ID will become :
2.8 mA
The official answer key records option 1, 2.8 mA. That figure cannot be produced by the circuit as printed, so the working is set out in full below and the discrepancy is stated plainly rather than papered over.
The circuit. The gate is tied back to the drain, so this is a diode-connected n-channel MOSFET with its source grounded. Two consequences follow immediately :
| Consequence | Why |
|---|---|
| \(V_{GS}=V_{DS}\) | Gate and drain are the same node |
| The device is always in saturation | Saturation needs \(V_{DS}\ge V_{GS}-V_{th}\); here \(V_{DS}=V_{GS}\), which exceeds \(V_{GS}-V_{th}\) for any positive \(V_{th}\) |
So the square-law applies throughout: \(I_{D}=k\left(V_{GS}-V_{th}\right)^{2}\).
Step 1 — extract k from the given operating point. With \(R_{D}=1\,\text{k}\Omega\) and \(I_{D}=4\,\text{mA}\),
\(V_{DS}=10-\left(4\,\text{mA}\right)\left(1\,\text{k}\Omega\right)=6\ \text{V}=V_{GS}\)
\(4=k\left(6-2\right)^{2}=16k\quad\Rightarrow\quad k=0.25\ \text{mA/V}^{2}\)
Step 2 — solve the load line with \(R_{D}=4\,\text{k}\Omega\). Writing \(V\) for the new \(V_{DS}=V_{GS}\), the device equation and the load line must hold together :
\(I_{D}=0.25\left(V-2\right)^{2}\qquad\text{and}\qquad I_{D}=\dfrac{10-V}{4}\)
\(0.25\left(V-2\right)^{2}=\dfrac{10-V}{4}\ \Rightarrow\ \left(V-2\right)^{2}=10-V\ \Rightarrow\ V^{2}-3V-6=0\)
\(V=\dfrac{3+\sqrt{33}}{2}\approx 4.37\ \text{V}\qquad\Rightarrow\qquad I_{D}=\dfrac{10-4.37}{4}\approx \mathbf{1.4\ mA}\)
Step 3 — the sanity check that settles the matter. Whatever the transistor does, the drain current has to flow through \(R_{D}\) from a 10 V rail. The absolute ceiling is reached only if the transistor were a short circuit:
\(I_{D(\max)}=\dfrac{10\ \text{V}}{4\ \text{k}\Omega}=2.5\ \text{mA}\)
2.8 mA exceeds that ceiling, and would require \(V_{DS}=10-2.8\times 4=-1.2\ \text{V}\) — a negative drain voltage from a positive supply. It is not a close call or a rounding question; the keyed value is unreachable.
The physical reasoning also points downward. Raising \(R_{D}\) from 1 kΩ to 4 kΩ drops more voltage across the resistor, which pulls the drain — and therefore the gate — lower, which reduces \(V_{GS}-V_{th}\) and so reduces the current. In a diode-connected device the current must fall when the load resistance rises. Option 1 is the only choice larger than the original 4 mA would allow after that fall, while 1.4 mA sits exactly where the algebra puts it.
Note on the recorded answer. The answer stored here follows the official key, as required. On the physics the defensible answer is option 3, 1.4 mA.
Similar Questions
The threshold voltage of an n-channel MOSFET can be increased by
Assertion (A) : MOS ICs based on MOSFET structure find wide applications in digital field.
Reason (R) : MOS ICs have small size and are easy to fabricate.
In MOSFET, the linear region current is :
(A) \(\dfrac{\mu_{n}C_{ox}w}{L}\left(V_{gs}-V_{th}-\dfrac{V_{ds}}{2}\right)V_{ds}\)
(B) \(\dfrac{\mu_{n}C_{ox}w}{L}\left(V_{gs}-V_{th}\right)V_{ds}\)
(C) \(\dfrac{\mu_{n}C_{ox}w}{2L}\left(V_{gs}-V_{th}\right)V_{ds}^{2}\)
(D) \(\dfrac{\mu_{n}C_{ox}w}{L}\left(V_{gs}-V_{th}\right)^{2}\)Choose the most appropriate answer from the options given below :
Approximate oxide capacitance value (Cgd) for saturation operating mode of MOS transistor is:
For an n-channel MOS transistor with $\mu_n$ = 600 cm2/Vs, Cox = 7 x 10-8 F/cm2, W = 40 $\mu_m$, L = 4$\mu_m$ and VTO=1.0 V, the value of K parameter is:
In MOS
A. The substrate fermi potential ϕF is negative in NMOS
B. The substrate fermi potential ϕF is positive in NMOS
C. The substrate bias voltage VSB is positive in NMOS, negative in PMOS
D. The substrate bias voltage VSB is negative in NMOS, positive in PMOS.
Choose the correct answer from the options given below:
In enhancement mode MOSFET the saturation (drain) current is given by
(a) \(K\dfrac{W}{L}(V_{gs}-V_{th})^{2}\)
(b) \(K\dfrac{W}{L}(V_{gs}-V_{th})(1+\lambda V_{ds})\)
(c) \(K\dfrac{W}{L}(V_{gs}-V_{th})^{2}(1+\lambda V_{ds})\)
(d) \(K\dfrac{W}{L}(V_{gs}-V_{th})^{2}(1-\lambda V_{ds})\)
Out of these
In a MOSFET the drain saturation current is
The threshold voltage of a MOSFET can be lowered by
1. using a thinner gate oxide
2. reducing the carrier concentration in the substrate
3. increasing the carrier concentration in the substrateOf these statements :
The threshold voltage of an n-channel MOSFET can be increased by
Important Questions from MOSFET
An n-channel MOSFET is connected as shown in the Figure.
Assume $V_{TH} = 1\text{ V}$, $V_{DD} = 5\text{ V}$, and $\mu C_{ox}\left(\frac{W}{L}\right) = 2\text{ mA V}^{-2}$ and neglect channel length modulation effects.
The gate voltage ($V_G$) of the n-channel MOSFET (in Volt) is __.
(rounded off to two decimal places)
- A semiconductor uses P-type substrates with $N_A = 5 \times 10^{15}cm^{-3}$ in an n-MOS device having depletion region width of 0.415 $\mu$m. What is the depletion charge in magnitude?
- MOSFETs exhibit a non-linear relationship between input voltage and output current due to the device construction. The non-linear relationship is connected through the device parameter 'K'. Calculate 'K' for a specific MOSFET operating with an input voltage of 6 V and output current of 10 mA. The Threshold voltage of the chosen MOSFET is 4 V.
- Given below are two statements: one is labelled as Assertion (a) and the other is labelled as Reason (r).
Assertion (a): In a ratioless logic, the transistors can be of minimum size.
Reason (r): In a ratioless logic, the logic levels are not dependent upon the relative device size. - What are the effects of increasing temperature in the I-V characteristics of the NMOS transistor ?
