Assertion (A) : The most commonly used amplifier in S/H circuit is unity gain NINV amplifier. Reason (R) : At the sampling state signal building is not desired.
Both (A) and (R) are true and (R) is the correct explanation of (A).
Both are true, and the reason states exactly why the gain is unity : a sample-and-hold must reproduce the input faithfully, not amplify it. The answer is option 1.
What a sample-and-hold does. A switch connects a hold capacitor to the input during the sample phase, so the capacitor charges to the input voltage; the switch then opens and the capacitor holds that value while the ADC converts it. Its purpose is to freeze a moving signal, not to change it — any gain would corrupt the value the converter is about to digitise, since the ADC's scale is fixed.
Why a unity-gain non-inverting amplifier is the right choice. The buffer is there for its impedance transformation, not for gain:
| Property | Value | Why it matters |
|---|---|---|
| Gain | Exactly 1 | The held value equals the sampled value |
| Input impedance | Very high | Draws almost no current from the capacitor |
| Output impedance | Very low | Drives the ADC without droop |
| Phase | Non-inverting | No sign change to undo |
The high input impedance is the critical specification. Once the switch opens, the only thing holding the value is charge on a small capacitor. Any current drawn from it makes the voltage fall — the droop rate:
\(\dfrac{dV}{dt}=\dfrac{I_{leak}}{C_{H}}\)
A FET-input op-amp with picoamp bias current keeps the droop to microvolts over the conversion time. A bipolar-input amplifier drawing nanoamps would lose far more than one LSB, so the buffer's input current, not its gain, is what the designer selects for.
Why the gain must be exactly one and not merely small. A non-inverting unity buffer is made by connecting the output directly to the inverting input — 100 % feedback, no resistors at all. Its gain is set by that connection rather than by a resistor ratio, so it is exact and drift-free, with no tolerance to contribute error. Any resistive divider would introduce a gain error that the converter would faithfully digitise.
The answer is flagged only because "signal building" is unusual phrasing for amplification; read that way, the reason is correct and does explain the assertion.
Hence, both (A) and (R) are true and (R) is the correct explanation of (A).
The output voltage (Vo) of the converter (IC 9400) is related to the input frequency (Fin) by the equation :
Using a 10‐bit conversion, the dynamic range available from an input signal sampled for 4 seconds at a sampling rate of 20 kHz is:
Arrange the following components of dual‐slot integrating A/D converter in order of their appearance while moving from input to output stage.
A. Comparator
B. Control
C. Integrator
D. Counter
Choose the correct answer from the options given below
The number of comparators in a parallel conversion type 8-bit A to D converter is
Resolution of Analog to Digital Converter ranging from -5V to +5V with 8 Bits coding is
Which one of the following is an element which samples the continuous signal into sequence pulses appearing at regular interval of time?