A hierarchical memory system that uses cache memory has cache access time of 50 nano seconds, main memory access time of 300 nano seconds, 75% of memory requests are for read, hit ratio of 0.8 for read access and the write-through scheme is used. What will be the average access time of the system both for read and write requests ?
157.5 n.sec.
In the write-through scheme every write updates main memory directly, so each write request costs the main memory access time, 300 ns. Only read requests benefit from the cache.
Read access: on a hit (probability 0.8) the word comes from the cache in 50 ns; on a miss (probability 0.2) the cache is checked first (50 ns) and then main memory is accessed (300 ns), i.e. 350 ns.
Average read time = \(0.8 \times 50 + 0.2 \times (50 + 300) = 40 + 70 = 110\) ns.
Write access time = 300 ns. Reads are 75% and writes are 25% of all requests.
Average access time = \(0.75 \times 110 + 0.25 \times 300 = 82.5 + 75 = 157.5\) ns. (110 ns is only the read average and 82.5 ns is only the read share, so neither covers both kinds of request.)
Hence, the answer is 157.5 n.sec..
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In _____ method, the word is written to the block in both the cache and main memory, in parallel.
Important Questions from Cache Memory
In advanced microprocessors, cache memories are used to
- The transformation of data from main memory to cache memory is referred as:
- Which of the following statements are true?
A. In the write-through policy, only the cache is updated
B. In the write-back policy, both cache and main memory are updated
C. Cache coherence problems exist in multiprocessors with private caches because of the need to share writable data
D. Cache coherence problem can be solved by means of hardware-only scheme
Choose the correct answer from the options given below: Consider a system with a processor and a 4 KB direct mapped cache with block size of 16 bytes. The system has a 16 MB physical memory. Four words P, Q, R, and S are accessed by the processor in the same order 10 times. That is, there are a total of 40 memory references in the sequence P, Q, R, S, P, Q, R, S, …….
Assume that the cache memory is initially empty. The physical addresses of the words are given below (1 word = 1 byte).
P: 0x845B32, Q: 0x845B26, R: 0x845B36, S: 0x846B32
Which of the following statements is/are true?
Note: 1K=$2^{10}$ and 1M=$2^{20}$- For a direct-mapped cache, 4 bits are used for the tag field and 12 bits are used to index into a cache block. The size of each cache block is one byte. Assume that there is no other information stored for each cache block.
Which ONE of the following is the CORRECT option for the sizes of the main memory and the cache memory in this system (byte addressable), respectively?
