Which ONE of the following is the CORRECT option for the sizes of the main memory and the cache memory in this system (byte addressable), respectively?
In computer memory systems, particularly caches, the memory address is typically divided into three parts: the Tag, the Index, and the Offset. This division helps in efficiently locating data.
For the given problem:
Since the cache block size is 1 byte, the number of bits required for the offset is $\log_2(\text{Block Size}) = \log_2(1) = 0$ bits. This means the offset part does not contribute to the address length in this specific scenario.
The total number of bits in a main memory address determines its size. The total address bits are the sum of the tag, index, and offset bits.
Total Address Bits = Tag bits + Index bits + Offset bits
Total Address Bits = 4 + 12 + 0 = 16 bits
Since the memory is byte addressable, the size of the main memory is $2^{\text{Total Address Bits}}$ bytes.
Main Memory Size = $2^{16}$ bytes
To express this in Kilobytes (KB), we use the conversion $1 \text{ KB} = 2^{10}$ bytes:
Main Memory Size = $2^{16} \text{ bytes} = 2^6 \times 2^{10} \text{ bytes} = 64 \times 1 \text{ KB} = 64 \text{ KB}
The size of the cache memory depends on the number of cache lines (determined by the index bits) and the size of each cache block.
Number of Cache Lines = $2^{\text{Index Bits}}$
Number of Cache Lines = $2^{12}$
The size of each cache block is given as 1 byte.
Cache Memory Size = (Number of Cache Lines) $\times$ (Size of each Cache Block)
Cache Memory Size = $2^{12} \times 1 \text{ byte} = 2^{12}$ bytes
To express this in Kilobytes (KB):
Cache Memory Size = $2^{12} \text{ bytes} = 2^2 \times 2^{10} \text{ bytes} = 4 \times 1 \text{ KB} = 4 \text{ KB}
Based on the calculations:
| Memory Type | Size |
|---|---|
| Main Memory | 64 KB |
| Cache Memory | 4 KB |
Therefore, the sizes of the main memory and the cache memory are 64 KB and 4 KB, respectively.
In advanced microprocessors, cache memories are used to
Consider a system with a processor and a 4 KB direct mapped cache with block size of 16 bytes. The system has a 16 MB physical memory. Four words P, Q, R, and S are accessed by the processor in the same order 10 times. That is, there are a total of 40 memory references in the sequence P, Q, R, S, P, Q, R, S, …….
Assume that the cache memory is initially empty. The physical addresses of the words are given below (1 word = 1 byte).
P: 0x845B32, Q: 0x845B26, R: 0x845B36, S: 0x846B32
Which of the following statements is/are true?
Note: 1K=$2^{10}$ and 1M=$2^{20}$
A hierarchical memory system that uses cache memory has cache access time of 50 nano seconds, main memory access time of 300 nano seconds, 75% of memory requests are for read, hit ratio of 0.8 for read access and the write-through scheme is used. What will be the average access time of the system both for read and write requests ?