The output of the circuit is given by :
\(A+B\)
Work forward gate by gate. The circuit has two identical halves feeding a final NAND, so simplify one half and the other follows by symmetry.
Step 1 — the upper half. The inverter gives \(\bar{A}\) and the NOR gives \(\overline{A+B}=\bar{A}\bar{B}\). The OR gate combines them:
\(Y_1=\bar{A}+\bar{A}\bar{B}\)
Apply the absorption law, \(X+XY=X\), with \(X=\bar{A}\):
\(Y_1=\bar{A}\)
Step 2 — the lower half. Identically, the inverter gives \(\bar{B}\), the NOR gives \(\overline{B+C}=\bar{B}\bar{C}\), and the OR gate produces
\(Y_2=\bar{B}+\bar{B}\bar{C}=\bar{B}\)
Notice that C has vanished completely — absorption swallowed the only branch that carried it. That is the key observation of the whole problem, and it immediately rules out options 1, 2 and 4, all of which contain C.
Step 3 — the output NAND.
\(Y=\overline{Y_1\cdot Y_2}=\overline{\bar{A}\cdot\bar{B}}\)
By De Morgan's theorem,
\(Y=\overline{\bar{A}}+\overline{\bar{B}}=A+B\)
Verify with a quick truth check. Take A = 0, B = 0, C = 1. Then \(Y_1=\bar{A}=1\) and \(Y_2=\bar{B}=1\), so the NAND gives 0 ✓, matching A + B = 0. Take A = 1, B = 0, C = 0: \(Y_1=0\), so the NAND gives 1 ✓, matching A + B = 1. Changing C never changes the output, confirming the redundancy.
The lesson. A NOR gate followed by an OR with one of its own inputs inverted is a redundant structure — the absorption law collapses it. Recognising \(X+XY=X\) and its dual \(X(X+Y)=X\) on sight is what turns a five-gate network into a single OR.
Hence, the output is A + B.
The Boolean expression \(AC+B\bar{C}\) is equivalent to :
Consider the following expressions :
(a) Y = f(A, B, C, D) = Σ (1, 2, 4, 7, 8, 11, 13, 14)
(b) Y = f(A, B, C, D) = Σ (3, 5, 7, 10, 11, 12, 13, 14)
(c) Y = f(A, B, C, D) = Π (0, 3, 5, 6, 9, 10, 12, 15)
(d) Y = f(A, B, C, D) = Π (0, 1, 2, 4, 5, 8, 9, 15)
Which of the above expressions are equivalent to the expression Y = A⊕B⊕C⊕D ?
In Boolean algebra, the term sum of products means
The value of \(\rm \overline{A+B}\) is :
The Boolean function Y = AB + CD is to be realized using only two-input NAND gates. The minimum number of gates required are:
The minimum number of 2-input NAND gates required to realize the logic function $Y = AB + \bar A \bar B$ is