The CPU of a system having 1 MIPS execution rate needs 4 machine cycles on an average for executing an instruction. The fifty percent of the cycles use memory bus. A memory read/ write employs one machine cycle. For execution of the programs, the system utilizes 90 percent of the CPU time. For block data transfer, an IO device is attached to the system while CPU executes the background programs continuously. What is the maximum IO data transfer rate if programmed IO data transfer technique is used ?
250 Kbytes/sec
In programmed I/O every byte is moved by the CPU itself, by executing instructions that test the device status, read the byte and store it in memory.
Instruction rate \(= 1\) MIPS \(= 10^{6}\) instructions/sec, with \(4\) machine cycles per instruction, so there are \(4 \times 10^{6}\) machine cycles/sec.
A programmed transfer of one byte costs about one instruction time of \(4\) machine cycles for the CPU-driven read and another for the memory write, together with status polling, i.e. about \(4\) instruction steps per byte.
Maximum rate \(= \frac{10^{6}}{4} = 250 \times 10^{3}\) bytes/sec \(= 250\) Kbytes/sec
Check: 2.2 Mbytes/sec is the cycle-stealing (DMA) style figure that uses free bus cycles, which programmed I/O cannot exploit, while 125 and 500 Kbytes/sec assume a different instruction count per byte.
Hence, 250 Kbytes/sec.
Similar Questions
A DMA controller transfers 32-bit words to memory using cycle Stealing. The words are assembled from a device that transmits characters at a rate of 4800 characters per second. The CPU is fetching and executing instructions at an average rate of one million instructions per second. By how much will the CPU be slowed down because of the DMA transfer ?
Arrange the given steps required for a Direct Memory Access (DMA) transfer in the correct order.
(A) Initiate DMA transfer request
(B) Transfer data directly between peripheral and memory
(C) Processor grants DMA control over the system bus
(D) DMA controller completes data transfer and signals completion
Choose the correct answer from the options given below :
Important Questions from Modes of Data Transfer
Which method bypasses the CPU for certain types of data transfer?
For long distance communication which of the following data transfer technique is used?
A DMA controller transfers 32-bit words to memory using cycle Stealing. The words are assembled from a device that transmits characters at a rate of 4800 characters per second. The CPU is fetching and executing instructions at an average rate of one million instructions per second. By how much will the CPU be slowed down because of the DMA transfer ?
Arrange the given steps required for a Direct Memory Access (DMA) transfer in the correct order.
(A) Initiate DMA transfer request
(B) Transfer data directly between peripheral and memory
(C) Processor grants DMA control over the system bus
(D) DMA controller completes data transfer and signals completion
Choose the correct answer from the options given below :
