Arrange the given steps required for a Direct Memory Access (DMA) transfer in the correct order. (A) Initiate DMA transfer request (B) Transfer data directly between peripheral and memory (C) Processor grants DMA control over the system bus (D) DMA controller completes data transfer and signals completion Choose the correct answer from the options given below :
(A), (C), (B), (D)
In DMA (Morris Mano), the DMA controller moves a block of data between an I/O device and memory without the CPU copying each word, after the CPU hands over the buses.
Step 1 — Initiate DMA transfer request (A): the controller raises Bus Request (BR) after the CPU has programmed the address, count and direction.
Step 2 — Processor grants DMA control over the system bus (C): the CPU finishes its current bus cycle, floats its buses and asserts Bus Grant (BG).
Step 3 — Transfer data directly between peripheral and memory (B): the controller drives the address and control lines and moves the block.
Step 4 — Completion (D): when the word count reaches zero the controller releases the bus and interrupts the CPU to signal the end of the transfer.
A grant cannot precede the request, so the sequences starting with the grant are wrong, and data cannot move on the bus before the grant, which rules out the order that transfers immediately after the request.
(A), (C), (B), (D) option is correct.
Similar Questions
A DMA controller transfers 32-bit words to memory using cycle Stealing. The words are assembled from a device that transmits characters at a rate of 4800 characters per second. The CPU is fetching and executing instructions at an average rate of one million instructions per second. By how much will the CPU be slowed down because of the DMA transfer ?
The CPU of a system having 1 MIPS execution rate needs 4 machine cycles on an average for executing an instruction. The fifty percent of the cycles use memory bus. A memory read/ write employs one machine cycle. For execution of the programs, the system utilizes 90 percent of the CPU time. For block data transfer, an IO device is attached to the system while CPU executes the background programs continuously. What is the maximum IO data transfer rate if programmed IO data transfer technique is used ?
Important Questions from Modes of Data Transfer
Which method bypasses the CPU for certain types of data transfer?
For long distance communication which of the following data transfer technique is used?
A DMA controller transfers 32-bit words to memory using cycle Stealing. The words are assembled from a device that transmits characters at a rate of 4800 characters per second. The CPU is fetching and executing instructions at an average rate of one million instructions per second. By how much will the CPU be slowed down because of the DMA transfer ?
The CPU of a system having 1 MIPS execution rate needs 4 machine cycles on an average for executing an instruction. The fifty percent of the cycles use memory bus. A memory read/ write employs one machine cycle. For execution of the programs, the system utilizes 90 percent of the CPU time. For block data transfer, an IO device is attached to the system while CPU executes the background programs continuously. What is the maximum IO data transfer rate if programmed IO data transfer technique is used ?
