Each item in List-II is the one word that identifies its circuit.

(a) A/D converter → (iii) successive approximation. This is the standard medium-speed conversion technique: a SAR performs a binary search, setting each bit from the MSB down, comparing an internal DAC output with the input at every step. An n-bit conversion takes exactly n clock cycles, independent of the input value.

(b) Emitter follower → (i) impedance matching. The common-collector stage has voltage gain just under unity but a very high input impedance \(\beta(r_{e}+R_{E})\) and a very low output impedance \(r_{e}+R_{S}/\beta\). It therefore takes a signal from a weak, high-impedance source and delivers it to a heavy load without loading the source — the definition of a buffer.

(c) Schmitt trigger → (iv) hysteresis. Positive feedback gives the comparator two different thresholds, an upper trip point for a rising input and a lower one for a falling input:

\(V_{UT},\ V_{LT}=\pm\dfrac{R_{2}}{R_{1}+R_{2}}V_{sat}\)

The gap between them is the hysteresis, and it is what stops a slowly changing or noisy input from producing multiple false transitions at the switching point.

(d) Phase locked loop → (ii) VCO. A PLL is three blocks — a phase detector, a loop filter and a voltage-controlled oscillator — connected in a loop. The phase detector compares input and VCO phases, the filtered error steers the VCO, and the loop settles when the two frequencies are locked.

The order (iii), (i), (iv), (ii) is option 2. Note that one certain link is enough here: only option 2 pairs the Schmitt trigger with hysteresis.

Hence, the correct match is (a)-(iii), (b)-(i), (c)-(iv), (d)-(ii).