The phase locked loop (PLL) is one of the interesting applications of the lock-in amplifier. Apart from FM stereo decoders, tracking filters, motor speed control, FM demodulators, etc. it has found wide applications in generation of local oscillator frequencies in house-hold TV and FM tuners as automatic frequency control (AFC). Indeed, PLL has emerged as one of the fundamental building blocks in electronics and it is commercially available as a single package. Basically, a PLL is a lock-in amplifier in which the reference signal is provided by its own output, converted to frequency by a voltage controlled oscillator (VCO). When locked to the input frequency the dc output is small but sufficient to drive the VCO to produce a frequency which is equal to that of the signal. In this tracking situation, the input signal and the VCO output are almost in phase quadrature and the lock-in amplifier produces a small dc voltage which is often referred to as error voltage. The moment input signal is fed, the VCO frequency starts changing and the PLL is said to be in the capture mode. The VCO continues to change its frequency until it equals that of the input and stays there ; the PLL is then in the phase-locked state. In this state, if there is any change in the input frequency, the loop automatically tracks it through its repetitive action.

 The name states the function: a voltage-controlled oscillator produces an output whose frequency is set by an input voltage. It is therefore a voltage-to-frequency converter — option 1.

\(f_{out}=f_{0}+K_{v}V_{c}\)

where \(f_{0}\) is the free-running frequency with no control voltage and \(K_{v}\) is the conversion gain in hertz per volt. Linearity of that relation over the working range is the VCO's principal specification.

How the conversion is achieved. Two families dominate:

Its role in the loop, as the passage describes. The phase detector compares the input signal with the VCO output and produces an error voltage; the loop filter smooths it; and the VCO converts that voltage back into a frequency. The loop therefore closes only because the VCO performs precisely this conversion — it is the element that turns the correction signal back into the quantity being controlled.

The complementary function belongs elsewhere. Frequency-to-voltage conversion — option 2 — is what the whole PLL performs when used as an FM demodulator: since the VCO's control voltage must track the input frequency, that control voltage is the demodulated output. Notice the neat inversion: a frequency-to-voltage converter is built by putting a voltage-to-frequency converter inside a feedback loop.

Where VCOs appear beyond the PLL: as the tuning element of a frequency synthesiser, as the modulator in a direct FM transmitter (where the audio signal is the control voltage), as the sweep source in a spectrum analyser, and as the clock generator in every digital system that must adjust its frequency.

Hence, the VCO performs voltage to frequency conversion.

 A PLL has three blocks, and the filter between the other two is a low-pass filter — option 3.

Why it must be low pass. A phase detector is essentially a multiplier, and multiplying two signals at \(f_{in}\) and \(f_{VCO}\) produces components at both the difference and the sum frequencies:

\(\cos A\cos B=\tfrac{1}{2}\cos(A-B)+\tfrac{1}{2}\cos(A+B)\)

Only the difference term carries the phase information the loop needs; when locked it becomes a DC level. The sum term, at roughly twice the carrier frequency, is useless and would frequency-modulate the VCO if allowed through. A low-pass filter passes the wanted DC and rejects the unwanted high-frequency product — the passage's "small dc voltage… referred to as error voltage".

The filter does far more than clean up the signal, though — it sets the loop's dynamics. Its bandwidth determines:

• the capture range, since the beat note must fall inside the filter's passband for the loop to pull in;
• the lock-in time, since a narrow filter responds slowly;
• the noise bandwidth, since a narrow filter rejects more input noise;
• the stability, since the filter contributes phase shift to a feedback loop that already has a pole from the VCO's integration.

The design compromise is therefore unavoidable: a wide filter captures quickly and tracks fast-changing inputs but admits noise and jitter; a narrow one is quiet and highly selective but slow to acquire and prone to losing lock. Most practical loops use a lag-lead network rather than a simple RC, so that the low-frequency gain needed for accuracy can be combined with the phase margin needed for stability.

Hence, a PLL contains a low pass filter.

 "Free-running" means exactly what it says: the loop has nothing to lock to, so the VCO runs at its own natural frequency. With no input signal there is no phase error, the phase detector produces no correction, and the VCO oscillates at \(f_{0}\) — the frequency set by its own R and C or L and C. That is option 4.

The three states of a PLL follow one another as a signal appears and is acquired:

The passage describes the transition between the last two: "the moment input signal is fed, the VCO frequency starts changing and the PLL is said to be in the capture mode… the VCO continues to change its frequency until it equals that of the input and stays there". Free running is the state before that sequence begins.

Two ranges characterise the loop, and the distinction matters:

• The capture range is the band of input frequencies, centred on \(f_{0}\), over which an unlocked loop can acquire lock. It is limited by the loop filter, since the beat note between input and VCO must pass through the filter to steer the VCO at all.
• The lock range is the band over which an already-locked loop can follow the input. It is wider, being limited only by the VCO's tuning range and the phase detector's output swing.

\(\text{Capture range}\le\text{Lock range}\)

always — it is easier to hold lock than to acquire it, which is why a loop that has slipped may not immediately recapture.

Why the other options are not states at all. They compare input and output voltages, but a PLL locks on frequency and phase; the amplitude relationship between input and VCO output is irrelevant to whether the loop is locked, since the input is typically limited or squared up before reaching the phase detector.

Hence, the PLL free-runs when no input is applied.

 A sample-and-hold circuit takes a brief look at a signal and then freezes that value, and freezing values is exactly what lets several signals share one channel in turn. That is time-division multiplexing — option 3.

How the circuit works. A switch (usually a FET or CMOS gate) connects the input to a hold capacitor for a short sampling interval, charging it to the instantaneous input voltage. The switch then opens and the capacitor retains that voltage, buffered by a high-input-impedance follower so that nothing discharges it:

\(\text{Droop rate}=\dfrac{dV}{dt}=\dfrac{I_{leakage}}{C_{H}}\)

— the specification that decides how long the value stays valid.

Why TDM needs it. In a TDM system each channel is sampled in rotation and its sample occupies one time slot on the shared line. The sample must be held steady while the multiplexer, the ADC or the line driver does its work, and each channel's value must persist until that channel's turn comes round again. Without a hold, the value would be gone before it could be used. The sampling rate for each channel must satisfy Nyquist,

\(f_{s}\ge2f_{m}\)

so a system with N channels must run its commutator at \(Nf_{s}\).

The other options are ruled out on function. FDM separates channels by shifting them to different frequencies, which needs mixers and filters, not a hold capacitor. Frequency and amplitude modulation are single-channel operations that alter a carrier's parameter continuously; neither requires a value to be frozen.

The other place a sample-and-hold is indispensable is at the input of an analog-to-digital converter. A SAR converter compares the input against its DAC output over n successive clock cycles, and the input must not move during that time — a change of even one LSB mid-conversion corrupts every bit still to be decided. Holding the sample makes the converted value correspond to one definite instant, which is also what makes the sampling time well defined for reconstruction.

Hence, sample-and-hold devices are used to perform time-division multiplexing.

 The PLL is the natural FM demodulator, and the reason is almost a restatement of what the loop does.

The argument in one step. When the loop is locked, the VCO frequency must follow the input frequency:

\(f_{VCO}=f_{in}\)

But the VCO's frequency is set by its control voltage,

\(f_{VCO}=f_{0}+K_{v}V_{c}\qquad\Rightarrow\qquad V_{c}=\dfrac{f_{in}-f_{0}}{K_{v}}\)

In an FM signal the instantaneous frequency is the message, so the control voltage is proportional to the message. The demodulated output is simply the voltage at the VCO input — no discriminator, no tuned circuits, no alignment. That is option 2.

Why the PLL displaced the older FM detectors. The Foster-Seeley discriminator and the ratio detector both rely on tuned transformers that must be aligned and that drift with temperature and age. A PLL demodulator has no tuned circuit at all, is available as a single IC, and gives markedly better linearity — hence lower distortion — because the loop forces the VCO to track rather than relying on the shape of a resonance curve.

Option 4 deserves comment, because a PLL genuinely does demodulate FSK — the 565 PLL's classic application is exactly that. But FSK is the digital special case of frequency modulation, so FM is the general and intended answer; a key expecting one answer must take the broader category.

The passage lists the same family of uses — FM stereo decoders, FM demodulators, AFC in tuners — all of which rest on this one property: a locked loop's control voltage is a faithful copy of the input's frequency variation.

Hence, a PLL is used to demodulate frequency modulated signals.