The bit-addressable area of the 8051's internal RAM is the sixteen bytes from 20H to 2FH — option 4.

How the 128 bytes are divided.

The arithmetic confirms the boundaries. Sixteen bytes hold

\(16\times8=128\ \text{bits}\)

and those bits are given their own addresses 00H to 7FH in a completely separate bit-address space. Bit 0 of byte 20H is bit address 00H, and bit 7 of byte 2FH is bit address 7FH. The overlap of numbers is a genuine source of confusion: address 20H in the byte space is the same physical location as bits 00H–07H in the bit space, and which is meant depends entirely on the instruction used.

Why options 1, 2 and 3 are wrong. All three fall inside 00H–1FH, which is the register-bank area. Those 32 bytes are the four switchable banks of R0–R7, selected by RS1 and RS0 in the PSW — they are directly addressable as bytes but not bit addressable.

What bit addressability buys. A single instruction can set, clear, complement or test one bit:

SETB 25H    CLR 2FH    JB 07H, label

Without it, changing one bit needs a read, a mask with AND or OR, and a write back — three instructions and a spare register, with the further hazard that an interrupt between the read and the write could lose a change made in between. The single-instruction form is atomic.

The feature extends beyond RAM. Special-function registers whose addresses are divisible by eight — P0, P1, P2, P3, TCON, SCON, IE, IP, PSW, ACC and B — are also bit addressable, which is what allows an individual port pin to be driven or tested directly. Together with the carry acting as a one-bit accumulator, this makes the 8051 unusually well suited to control work.

Hence, the bit-addressable area is 20H–2FH.