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Question

In a JK flip flop, the J input mainly performs which function when K = 0 and the clock is active?

This question was previously asked in
RRB ALP 2025 CBT 2 Wiremen Question Paper (28-Jul-2026) (Shift 2)
The correct answer is

The Set input

The question pertains to the functioning of a JK flip-flop, a fundamental sequential logic circuit used in various electronic applications. To determine the role of the J input in a JK flip-flop when K = 0 and the clock is active, let's explore its operational characteristics:

At its core, a JK flip-flop is a modified version of an SR flip-flop with added control against invalid states. Its working mechanism is based on two inputs, J and K, along with a clock signal. The behavior of these inputs governs the output state of the flip-flop.

  1. When both J and K are 0, the output state remains unchanged.
  2. When J = 1 and K = 0, the output state (Q) is set to 1. This indicates that the J input functions as the Set input.
  3. When J = 0 and K = 1, the output state (Q) is reset to 0. In this case, the K input serves as the Reset input.
  4. When both J and K are 1, the flip-flop toggles its current state (i.e., if it was 0, it becomes 1, and vice-versa).

Given this operation table, when K = 0 and the clock is active, the J input is responsible for setting the output to 1. Hence, the J input functions as the Set input when K = 0.

Therefore, the correct answer to the question is: The Set input.

Let's analyze the options to ensure clarity:

  • The Set input: Correct, as explained above, since J = 1 sets the output state when K = 0.
  • The Reset input: Incorrect, because the reset function is controlled by the K input when J = 0.
  • The Clock input: Incorrect, as the clock input does not directly perform setting or resetting functions but rather synchronizes state changes based on J and K values.
  • The Toggle input: Incorrect, as toggling occurs when both J and K are 1, which is not the scenario in this question.
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Similar Questions

  1. Race around condition can be removed by using the combination of:

  2. Counter design can be implemented by:

  3. During a laboratory test, a trainee builds an RS flip-flop using NOR gates (active-HIGH inputs). Initially, the output Q = 0. The trainee applies S = 1 (Set input) and R = 0 (Reset input). After this, both inputs are returned to S = 0 and R = 0. What will happen to the output Q?


Important Questions from Flip Flops and Counters

  1. Race around condition can be removed by using the combination of:

  2. A JK flip flop with J = K = 1 has a 100 kHz clock input. The Q output is

  3. A ring counter with 5 flip-flops will have:

  4. A 4 bit counter is used to count form 0, 1, 2 …. n. Value of ‘n’ is

  5. Counter design can be implemented by:

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