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Question

During a laboratory test, a trainee builds an RS flip-flop using NOR gates (active-HIGH inputs). Initially, the output Q = 0. The trainee applies S = 1 (Set input) and R = 0 (Reset input). After this, both inputs are returned to S = 0 and R = 0. What will happen to the output Q?

This question was previously asked in
RRB ALP 2025 CBT 2 Wiremen Question Paper (28-Jul-2026) (Shift 2)
The correct answer is

Q will remain at 1 after inputs become 0, holding the last state.

In this problem, we are dealing with an RS flip-flop created using NOR gates and analyzing how the output Q changes based on specific inputs. Let's break down the problem step-by-step:

  1. The RS flip-flop is made using NOR gates, which means it is a simple bistable multivibrator.
  2. Initially, the output Q is given as 0 (Q = 0).
  3. The inputs provided are S = 1 (Set input) and R = 0 (Reset input). When S = 1 and R = 0 are applied to an RS flip-flop:
    • The flip-flop will set the output to Q = 1, because the set input (S) is high and the reset input (R) is low.
  4. After setting S = 1 and R = 0, both inputs are returned to S = 0 and R = 0. For a NOR gate-based RS flip-flop:
    • When S = 0 and R = 0, the flip-flop holds its last state. Therefore, the output Q will remain 1.

Therefore, after applying the sequence of inputs, the output Q remains at 1, holding the last state when the inputs become S = 0 and R = 0.

Thus, the correct answer is: Q will remain at 1 after inputs become 0, holding the last state.

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Similar Questions

  1. Race around condition can be removed by using the combination of:

  2. Counter design can be implemented by:

  3. In a JK flip flop, the J input mainly performs which function when K = 0 and the clock is active?


Important Questions from Flip Flops and Counters

  1. Race around condition can be removed by using the combination of:

  2. A JK flip flop with J = K = 1 has a 100 kHz clock input. The Q output is

  3. A ring counter with 5 flip-flops will have:

  4. A 4 bit counter is used to count form 0, 1, 2 …. n. Value of ‘n’ is

  5. Counter design can be implemented by:

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