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Question

Given a computing system with two levels of cache (L1 and L2) and a main memory. The first level (L1) cache access time is 1 nanosecond (ns) and the “hit rate" for L1 cache is 90% while the processor is accessing the data from L1 cache. Whereas, for the second level (L2) cache, the “hit rate" is 80% and the "miss penalty" for transferring data from L2 cache to L1 cache is 10 ns. The “miss penalty" for the data to be transferred from main memory to L2 cache is 100 ns.

Then the average memory access time in this system in nanoseconds is ____________ (rounded off to one decimal place)

To determine the average memory access time (AMAT) for the given computing system, we need to consider the hierarchical structure of the caches and their respective hit/miss rates and penalties. The formula for AMAT when considering multiple levels of cache is:

AMAT = L1 hit time + (L1 miss rate × (L2 hit time + L2 miss rate × memory access time))

Let's break this down into steps:

Step 1: Define the variables
L1 hit time = 1 ns (accessing data from L1 cache)
L1 hit rate = 90% = 0.9
L1 miss rate = 1 - 0.9 = 0.1
L2 hit time = 10 ns (miss penalty for L2 cache)
L2 hit rate = 80% = 0.8
L2 miss rate = 1 - 0.8 = 0.2
Main memory access time = 100 ns (miss penalty for main memory)

Step 2: Compute the effective L2 access time
For L2: Hit occurs 80% of the time, accounting for 10 ns. Miss incurs an additional 100 ns penalty:
Effective L2 access time = L2 hit time + L2 miss rate × memory access time
= 10 ns + 0.2 × 100 ns = 10 ns + 20 ns = 30 ns

Step 3: Compute the AMAT
Substitute the effective L2 access time into the AMAT formula:
AMAT = 1 ns + 0.1 × 30 ns
= 1 ns + 3 ns = 4 ns

Step 4: Verify the result
The computed AMAT is 4 ns, which falls within the expected range of 4 to 4 as specified. Thus, the solution is validated.
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Important Questions from Memory Hierarchy

  1. Suppose that the register A and register K have the bit configuration. Only the three leftmost bits of A are compared with memory words because K has 1's in these positions. Because of its organization, this type of memory is uniquely suited to parallel searches by data association. This type of memory is known as

  2. Consider a system with 2 level cache. Access times of Level 1, Level 2 cache and main memory are 0.5 ns, 5 ns and 100 ns respectively. The hit rates of Level 1 and Level 2 caches are 0.7 and 0.8 respectively. What is the average access time of the system ignoring the search time within cache?

  3. Related to computers, what is 'Wetware'?

  4. ____ number of lines are required to select __________ memory locations.

  5. A computer has a memory hierarchy consisting of two-level cache (L1 and L2) and a main memory. If the processor needs to access data from memory, it first looks into L1 cache. If the data is not found in L1 cache, it goes to L2 cache. If it fails to get the data from L2 cache, it goes to main memory, where the data is definitely available. Hit rates and access times of various memory units are shown in the figure. The average memory access time in nanoseconds (ns) is ________. (rounded off to two decimal places)

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