Only (C) and (D) are correct — option 4.

(C) is the standard overflow rule, and it is exact. For signed two's-complement addition,

\(V=C_{in,sign}\oplus C_{out}\)

Overflow occurs when the carry into the sign bit differs from the carry out of it. The reason is that if the two disagree, the sign bit has been changed by a carry that the result cannot represent — two positives have produced a negative, or two negatives a positive.

(A) is wrong because a carry alone proves nothing. Adding two negative numbers in two's complement almost always produces a carry out, yet the result is usually perfectly valid. Consider −1 + −1 in four bits:

\(1111+1111=1\,1110\)

There is a carry out, and the result 1110 is −2, which is correct. A carry by itself is meaningful for unsigned arithmetic; for signed arithmetic only the comparison in (C) will do. This is exactly why processors provide both a carry flag and a separate overflow flag.

(B) is refuted by a single example. In four bits, −8 plus −8:

\(1000+1000=1\,0000\)

The four-bit result is 0000, that is zero — plainly wrong, since −16 lies outside the range −8 to +7. Overflow certainly can occur with two negatives; the rule is only that it cannot occur when the operands have opposite signs, since the magnitude of such a sum can never exceed either operand.

(D) is a plain statement of fact. A full adder takes A, B and C_in and produces

\(S=A\oplus B\oplus C_{in},\qquad C_{out}=AB+C_{in}\left(A\oplus B\right)\)

— three inputs, two outputs, adding three bits at a time. The third input is what allows full adders to be chained into a ripple-carry adder of any width, which a half adder cannot do.

A useful summary of the signed rules : overflow is impossible when the signs differ; when the signs agree, overflow has occurred if the result's sign differs from theirs.

Hence, the correct statements are (C) and (D).