The period, T = 64 microseconds = 64×10-6 seconds. Hence, frequency at the last flip-flop: f = 1/64×10-6 Hz = 15,625 Hz.
Since this is for the last flip-flop which divides the frequency by 16, the input frequency (fin) is:
fin = 15,625 Hz × 16 = 250,000 Hz = 250 kHz.
This result of 250 kHz must be within the given expected range of 250,250, which it is. Therefore, the frequency of the ripple counter in kHz is 250.
Important Questions from Counter
Which of the following is not capable of storing binary data?
A _________ is a register capable of counting the number of clock pulses arriving at its clock input.
A MOD 2 and a MOD 5 up-counter when cascaded together results in a MOD ______ counter. (in integer)
A counter is constructed with three D flip-flops. The input-output pairs are named (D0, Q0), (D1, Q1), and (D2, Q2), where the subscript 0 denotes the least significant bit. The output sequence is desired to be the Gray-code sequence 000, 001, 011, 010, 110, 111, 101, and 100, repeating periodically. Note that the bits are listed in the Q2 Q1 Q0 format. The combinational logic expression for D1 is
A 16-bit synchronous binary up-counter is clocked with a frequency fCLK. The two most significant bits are OR-ed together to form an output Y. Measurements show that Y is periodic, and the duration for which Y remains high in each period is 24 ms. The clock frequency fCLK is ______ MHz. (Round off 2 decimal places.)
