(a) LOAD input is high
(b) $\overline{\text{LOAD}}$ input is high
(c) CLEAR is high
(d) Enable input is low
Out of the above, the following is the correct answer :
This explanation details the necessary conditions for a digital counter to function correctly when counting upwards from an initial state of 0000.
To achieve an upwards count starting from 0000, specific control signals must be active:
Statement (b) $\overline{\text{LOAD}}$ input is high: This condition signifies that the $LOAD$ input is low. A low $LOAD$ input usually prevents loading data. As the correct configuration requires the $LOAD$ input to be high (statement a) to set the initial state, this condition (b) is incompatible and thus incorrect for this specific counting requirement.
Therefore, the combination of statements (a), (c), and (d) represents the required conditions for the counter to count upwards from 0000.
Race around condition can be removed by using the combination of:
A JK flip flop with J = K = 1 has a 100 kHz clock input. The Q output is
A ring counter with 5 flip-flops will have:
A 4 bit counter is used to count form 0, 1, 2 …. n. Value of ‘n’ is
Counter design can be implemented by: