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Question

During the Instruction Cycle, which specific register holds the instruction that is currently being decoded and executed by the CPU?

This question was previously asked in
SSC CGL 2025 Tier 1 Question Paper (25-Sep-2025) (Shift 3)
The correct answer is

Instruction Register (IR)

During the instruction cycle the CPU repeatedly fetches an instruction from memory, decodes what it means, and then executes it.

Once an instruction is fetched, it is placed into the Instruction Register (IR), where it is held while the control unit decodes it and carries out the required operation.

So the register that holds the instruction currently being decoded and executed is the Instruction Register (IR).

The Program Counter (PC) does not hold the current instruction; it holds the memory address of the next instruction to be fetched.

The Memory Address Register (MAR) holds the address of the memory location being read or written during a memory access, and the Accumulator (AC) holds operands or the results of arithmetic and logic operations.

Only the IR actually stores the instruction being processed at that moment, which is why it is the correct answer.

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Important Questions from Machine Instructions and Addressing Modes

  1. Arrange the following types of machine in descending order of complexity.

    (A) SISD

    (B) MIMD

    (C) SIMD

    Choose the correct answer from the options given below:

  2. Consider the following program fragment in assembly language:

    mov ax, 0h

    mov cx, 0A h

    doloop:

    dec ax

    loop doloop

    What is the value of ax and cx registers after the completion of the doloop?

  3. Consider the following assembly program fragment:

    stc

    mov al, 11010110b

    mov cl, 2

    rcl al, 3

    rol al, 4

    shr al, cl

    mul cl

    The contents of the destination register ax (in hexadecimal) and the status of Carry Flag (CF) after the execution of above instructions, are:

  4. A micro-instruction format has micro-ops field which is divided into three subfields F1, F2, F3 each having seven distinct micro-operations, condition field CD for four status bits, branch field BR having four options used in conjunction with address field ADF. The address space is of 128 memory locations. The size of micro-instruction is :  

  5. This instruction is of what type?

    ADD R1, A, B

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