This instruction is of what type? ADD R1, A, B
Three Address Instruction
Analyzing Computer Instruction Types: ADD R1, A, B
The question asks to identify the type of instruction represented by "ADD R1, A, B". Understanding different instruction formats in computer architecture is key to solving this.
Instructions can be classified based on the number of addresses (operands) they explicitly specify. Common types include:
- Zero-Address Instructions: These instructions typically operate on operands found at the top of a stack. The operands are implicitly defined by the stack structure. An example is simply "ADD", which would add the top two elements of the stack and push the result back onto the stack.
- One-Address Instructions: These instructions often use an implicit accumulator register. One operand is in the accumulator, and the other is specified in the instruction (either a memory address or another register). An example is "ADD A", which might mean Add the value at memory location A to the Accumulator (Acc = Acc + A).
- Two-Address Instructions: These instructions specify two operands. Typically, one operand serves as both a source and the destination for the result. An example is "ADD R1, A", which could mean Add the value at memory location A to register R1 and store the result in R1 (R1 = R1 + A).
- Three-Address Instructions: These instructions specify three operands: two source operands and one destination operand. The operation is performed on the two source operands, and the result is stored in the destination operand.
Examining the Instruction: ADD R1, A, B
Let's look closely at the given instruction: ADD R1, A, B.
- ADD is the operation (addition).
- R1 is the first operand. This operand typically serves as the destination where the result will be stored.
- A is the second operand. This is a source operand.
- B is the third operand. This is also a source operand.
The instruction structure implies that the operation is performed on operands A and B, and the result is stored in R1. Mathematically, this can be represented as:
\(R1 = A + B\)
Since the instruction explicitly specifies three operands (R1, A, and B), it falls under the category of a Three Address Instruction.
Comparison of Instruction Types
| Instruction Type | Number of Addresses | Typical Format Example | Meaning Example |
|---|---|---|---|
| Zero Address | 0 | ADD | Stack[Top] <- Stack[Top] + Stack[Top-1]; Pop two, Push one |
| One Address | 1 | ADD A | Acc <- Acc + Memory[A] |
| Two Address | 2 | ADD R1, A | R1 <- R1 + Memory[A] or R1 <- R1 + R2 |
| Three Address | 3 | ADD R1, A, B | R1 <- Memory[A] + Memory[B] or R1 <- R2 + R3 |
Based on this analysis, the instruction ADD R1, A, B is clearly a Three Address Instruction because it has three explicit operands.
Revision Table: Instruction Format Types
| Instruction Format | Operand Count | Mechanism |
|---|---|---|
| Zero Address | 0 | Stack-based operation |
| One Address | 1 | Accumulator-based operation |
| Two Address | 2 | Source/Destination explicit |
| Three Address | 3 | Two sources, one destination explicit |
Additional Information: CPU Instruction Formats
Instruction formats are a fundamental part of CPU design. The format determines how the opcode and operands are arranged within an instruction word. The number of addresses is a key characteristic of the instruction format and directly impacts the length of the instruction and the complexity of the addressing modes and the CPU's control unit. Three-address instructions are more complex but can perform operations in a single instruction that might require multiple instructions in zero, one, or two-address architectures, potentially leading to shorter programs (fewer instructions) though individual instructions might be longer.
Modern computer architectures, like RISC (Reduced Instruction Set Computing) processors, often use a fixed-length instruction format and commonly employ three-address instructions for arithmetic and logic operations, typically operating on registers.
Important Questions from Machine Instructions and Addressing Modes
Arrange the following types of machine in descending order of complexity.
(A) SISD
(B) MIMD
(C) SIMD
Choose the correct answer from the options given below:
Consider the following program fragment in assembly language:
mov ax, 0h
mov cx, 0A h
doloop:
dec ax
loop doloop
What is the value of ax and cx registers after the completion of the doloop?
Consider the following assembly program fragment:
stc
mov al, 11010110b
mov cl, 2
rcl al, 3
rol al, 4
shr al, cl
mul cl
The contents of the destination register ax (in hexadecimal) and the status of Carry Flag (CF) after the execution of above instructions, are:
A micro-instruction format has micro-ops field which is divided into three subfields F1, F2, F3 each having seven distinct micro-operations, condition field CD for four status bits, branch field BR having four options used in conjunction with address field ADF. The address space is of 128 memory locations. The size of micro-instruction is :
The following language uses mnemonic OP codes
