Understanding 8085 Microprocessor Interrupts

The 8085 microprocessor is designed to handle various events that require immediate attention, known as interrupts. Interrupts are signals that temporarily stop the execution of the current program and transfer control to a special routine called an Interrupt Service Routine (ISR). After the ISR completes its task, the microprocessor returns to executing the original program from where it was interrupted.

8085 interrupts can be broadly classified into two categories: maskable and non-maskable.

• Maskable Interrupts: These are interrupts that can be enabled or disabled by the programmer using instructions like DI (Disable Interrupts) and EI (Enable Interrupts). If a maskable interrupt is disabled, the microprocessor will ignore the interrupt request.
• Non-Maskable Interrupts: These are interrupts that cannot be disabled by the programmer using software instructions. They are typically reserved for critical events that require immediate attention, such as power failure or a system crash. The microprocessor will always respond to a non-maskable interrupt, regardless of the interrupt enable flag status.

Analyzing 8085 Interrupt Types

The 8085 microprocessor has several interrupt inputs. Let's examine the nature of the interrupts provided in the options:

• RST 6.5: This is a hardware interrupt pin on the 8085. It is a maskable interrupt. Its interrupt request can be masked (ignored) by setting a specific bit in the interrupt mask register using the SIM instruction. It has a fixed vector address.
• TRAP: This is a hardware interrupt pin on the 8085. It is a non-maskable interrupt. This means its request cannot be disabled by software instructions like DI or the SIM instruction. It is the highest priority interrupt among the 8085's hardware interrupts and has a fixed vector address.
• RST 5.5: This is another hardware interrupt pin on the 8085. Like RST 6.5, it is a maskable interrupt. Its request can be masked using the SIM instruction. It also has a fixed vector address.
• INTR: This is the general-purpose hardware interrupt pin on the 8085. It is a maskable interrupt. Its request can be enabled or disabled by the EI and DI instructions. It is the lowest priority hardware interrupt. Unlike the other hardware interrupts (RST 5.5, 6.5, 7.5, TRAP) which are vectored, the vector address for INTR is provided by the interrupting device through the data bus using the INTA (Interrupt Acknowledge) signal.

Identifying Non-Maskable Interrupts in 8085

Based on the analysis above, we can see that among the given options, TRAP is the only non-maskable interrupt. The 8085 microprocessor is designed to always respond to an interrupt signal on the TRAP pin, making it suitable for handling critical system events.

Summary of 8085 Hardware Interrupts

Here is a summary of the built-in hardware interrupts in the 8085:

The vector address is the memory location where the corresponding Interrupt Service Routine (ISR) is assumed to begin. For vectored interrupts (TRAP, RST 5.5, 6.5, 7.5), the 8085 automatically jumps to the fixed vector address upon acknowledging the interrupt.

Revision Table: 8085 Interrupt Properties

Additional Information: 8085 Interrupt Handling

Interrupt handling involves several steps:

• Interrupt Request: An external device or an internal event signals the CPU.
• Interrupt Acknowledge: The CPU completes its current instruction and checks for interrupts. If an interrupt is recognized and is enabled (for maskable interrupts), the CPU acknowledges the request.
• Saving Context: The CPU saves the current state, typically the program counter (PC), onto the stack so it can return to the interrupted program later.
• Vectoring: The CPU determines the starting address of the ISR. For vectored interrupts like TRAP, RST 5.5/6.5/7.5, this address is fixed. For INTR, the device provides the address (or an instruction byte).
• Executing ISR: The CPU jumps to the ISR address and executes the routine. The ISR performs the necessary task to handle the interrupt source.
• Returning from ISR: The ISR usually ends with a RET (Return) instruction. This instruction pops the saved PC value from the stack, allowing the CPU to return to the instruction it was about to execute before the interrupt occurred.

The SIM (Set Interrupt Mask) and RIM (Read Interrupt Mask) instructions are crucial for managing maskable interrupts (RST 5.5, 6.5, 7.5) in the 8085. The DI (Disable Interrupts) and EI (Enable Interrupts) instructions affect the overall interrupt enable flip-flop, which controls whether maskable interrupts are generally allowed.