8085 Microprocessor ROM Addressing: Understanding Chip Select Logic

The question asks us to find the correct logic expression for the active low Chip Select (\(\overline{{\rm{CS}}}\)) signal for an 8 Kbyte ROM used with an 8085 microprocessor. The ROM needs to occupy the address range from 1000H to 2FFFH.

Address Range Analysis for 8 Kbyte ROM

First, let's analyze the given address range and the size of the ROM:

• ROM Size: 8 Kbytes. This means the ROM has \(8 \times 1024 = 8192\) unique memory locations. To address 8192 locations, we need \(\log_2(8192) = 13\) address lines (typically A0 to A12).
• Given Address Range: 1000H to 2FFFH.

Let's convert the start and end addresses into their 16-bit binary representations (A15 to A0):

• Start Address (1000H):
  0001 0000 0000 0000 (A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0)
• End Address (2FFFH):
  0010 1111 1111 1111 (A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0)

Now, let's observe the most significant address bits (A15, A14, A13, A12) across this entire range:

From the table, we can deduce the following conditions for the ROM to be selected (i.e., for an address within the 1000H to 2FFFH range):

• Address bit A15 must be 0.
• Address bit A14 must be 0.
• Address bits A13 and A12 must be different (either A13=0, A12=1 OR A13=1, A12=0). This is the behavior of an XOR (Exclusive OR) gate. So, \(A_{13} \oplus A_{12} = 1\).
• Address bits A0 through A11 are the internal address lines for the 8 Kbyte ROM and are "don't care" for the chip select decoding logic.

Deriving the Chip Select (\(\overline{{\rm{CS}}}\)) Logic Expression

The \(\overline{{\rm{CS}}}\) signal is an active low input, meaning the ROM is selected when \(\overline{{\rm{CS}}}\) is LOW (0). Based on our address analysis, \(\overline{{\rm{CS}}}\) should be LOW if:

1. A15 is 0 (LOW), AND
2. A14 is 0 (LOW), AND
3. A13 and A12 are different (A13 XOR A12 is HIGH).

Let's represent the conditions for ROM selection (when \(\overline{{\rm{CS}}}\) should be 0) using Boolean algebra. If 'S' represents the condition for selection (i.e., S=1 when selected):

\[ S = \overline{A_{15}} \cdot \overline{A_{14}} \cdot (A_{13} \cdot \overline{A_{12}} + \overline{A_{13}} \cdot A_{12}) \]

Since \(\overline{{\rm{CS}}}\) is active low, \(\overline{{\rm{CS}}}\) should be the complement of S (\(\overline{{\rm{CS}}} = \overline{S}\)). Applying De Morgan's theorem:

\[ \overline{{\rm{CS}}} = \overline{\overline{A_{15}} \cdot \overline{A_{14}} \cdot (A_{13} \cdot \overline{A_{12}} + \overline{A_{13}} \cdot A_{12})} \]

\[ \overline{{\rm{CS}}} = \overline{\overline{A_{15}}} + \overline{\overline{A_{14}}} + \overline{(A_{13} \cdot \overline{A_{12}} + \overline{A_{13}} \cdot A_{12})} \]

We know that \(\overline{(A \cdot \overline{B} + \overline{A} \cdot B)}\) is the complement of XOR, which is XNOR. The XNOR operation \(A \odot B\) can be written as \((A \cdot B + \overline{A} \cdot \overline{B})\).

Therefore, the expression for \(\overline{{\rm{CS}}}\) becomes:

\[ \overline{{\rm{CS}}} = A_{15} + A_{14} + (A_{13} \cdot A_{12} + \overline{A_{13}} \cdot \overline{A_{12}}) \]

Evaluating the Given Options

Let's check the provided options against our derived expression for \(\overline{{\rm{CS}}}\):

• Option 1: \(A_{15} + A_{14} + (A_{13} \cdot A_{12} + \overline{A_{13}} \cdot \overline{A_{12}})\)

  For \(\overline{{\rm{CS}}}\) to be LOW (0), the entire OR expression must evaluate to 0. This requires each term in the OR expression to be 0:

  1. \(A_{15}\) must be 0.
  2. \(A_{14}\) must be 0.
  3. \((A_{13} \cdot A_{12} + \overline{A_{13}} \cdot \overline{A_{12}})\) must be 0. This term represents an XNOR gate. An XNOR gate outputs 0 only when its inputs are different. So, A13 and A12 must be different (i.e., A13=0, A12=1 OR A13=1, A12=0).

  These conditions (A15=0, A14=0, A13 \(\neq\) A12) exactly match the requirements for the ROM's address range. Therefore, this expression correctly generates the active low \(\overline{{\rm{CS}}}\) signal.

• Option 2: \(A_{15} \cdot A_{14} \cdot (A_{13} + A_{12})\)

  For this expression to be 0 (active low \(\overline{{\rm{CS}}}\)), it requires either \(A_{15}\) or \(A_{14}\) or \((A_{13} + A_{12})\) to be 0. However, if this expression is meant to be the condition for selection, then if it evaluates to 1, \(\overline{{\rm{CS}}}\) should be low. For it to be 1, \(A_{15}\) must be 1 and \(A_{14}\) must be 1, which contradicts our requirement that \(A_{15}\) and \(A_{14}\) must be 0.

• Option 3: \(\overline{A_{15}} \cdot \overline{A_{14}} \cdot (A_{13} \cdot \overline{A_{12}} + \overline{A_{13}} \cdot A_{12})\)

  This expression represents the exact conditions for the ROM to be selected (output is 1 when address is in range). If this were directly connected to an active low \(\overline{{\rm{CS}}}\) input, it would mean \(\overline{{\rm{CS}}}\) becomes 1 (high) when the address is in range, which is incorrect. For an active low \(\overline{{\rm{CS}}}\), we need the complement of this expression, which we derived as Option 1.

• Option 4: \(\overline{A_{15}} + \overline{A_{14}} + (A_{13} \cdot A_{12})\)

  For this OR expression to be 0 (active low \(\overline{{\rm{CS}}}\)), each term must be 0. This means \(\overline{A_{15}}=0\) (so \(A_{15}=1\)) and \(\overline{A_{14}}=0\) (so \(A_{14}=1\)), which contradicts our requirement that A15 and A14 must be 0.

Based on our detailed analysis, Option 1 is the correct logic expression to generate the \(\overline{{\rm{CS}}}\) signal for the given ROM and address range.