A computer uses a memory unit of 512 K words of 32 bits each. A binary instruction code is stored in one word of the memory. The instruction has four parts: an addressing mode field to specify one of the two-addressing mode (direct and indirect), an operation code, a register code part to specify one of the 256 registers and an address part. How many bits are there in addressing mode part, opcode part, register code part and the address part?
1, 4, 8, 19
Understanding Computer Instruction Format and Memory Addressing
Let's break down the structure of the computer instruction based on the given memory unit specifications. We are given a memory unit with 512 K words, where each word is 32 bits long. A binary instruction code is stored in one word, meaning the instruction length is 32 bits. The instruction is divided into four main parts:
- Addressing mode field
- Operation code (Opcode)
- Register code part
- Address part
We need to determine the number of bits allocated to each of these parts.
Calculating Bits for Each Instruction Part
1. Addressing Mode Field
The problem states that the addressing mode field specifies one of two addressing modes: direct and indirect. To distinguish between two possibilities, we need a minimum number of bits. The number of bits required is calculated using the formula: $bits = \log_2(\text{number of options})$.
Number of addressing modes = 2
Bits for addressing mode = $\log_2(2) = 1$ bit.
2. Register Code Part
The register code part is used to specify one of 256 registers. Similar to the addressing mode, the number of bits required is $\log_2(\text{number of registers})$.
Number of registers = 256
We know that $2^8 = 256$.
Bits for register code = $\log_2(256) = 8$ bits.
3. Address Part
The address part of the instruction is used to address a location in memory. The memory unit has 512 K words. We need to determine how many bits are required to uniquely address each word in this memory.
- Memory size = 512 K words
- 1 K = $2^{10}$
- 512 = $2^9$
So, 512 K words = $512 \times 1024$ words = $2^9 \times 2^{10}$ words = $2^{(9+10)}$ words = $2^{19}$ words.
To address $2^{19}$ unique locations, we need 19 bits ($2^{19}$ distinct addresses require 19 bits).
Bits for address part = 19 bits.
4. Operation Code (Opcode)
The total length of the instruction is given as 32 bits (since it is stored in one word of the 32-bit memory). The instruction is made up of the addressing mode, opcode, register code, and address parts. The sum of the bits for all these parts must equal the total instruction length.
Total instruction length = 32 bits
Bits used by other parts = Bits for addressing mode + Bits for register code + Bits for address part
Bits used by other parts = 1 bit + 8 bits + 19 bits = 28 bits.
Bits for opcode = Total instruction length - Bits used by other parts
Bits for opcode = 32 bits - 28 bits = 4 bits.
Summary of Bit Allocation
Let's summarize the number of bits for each part of the instruction:
| Instruction Part | Number of Bits |
|---|---|
| Addressing Mode | 1 |
| Opcode | 4 |
| Register Code | 8 |
| Address Part | 19 |
| Total | 32 |
The question asks for the number of bits in the addressing mode part, opcode part, register code part, and the address part, in that specific order.
The number of bits are 1, 4, 8, and 19 respectively.
Revision Table: Computer Instruction Format Bits
Understanding the components of an instruction and how their size is determined based on system architecture details like memory size and register count is fundamental.
| Instruction Component | Dependency | Calculation Basis | Example (from question) |
|---|---|---|---|
| Addressing Mode Field | Number of modes | $\log_2(\text{Number of modes})$ | 2 modes $\implies \log_2(2) = 1$ bit |
| Opcode | Total instruction length, size of other fields | Total Length - Sum of other field sizes | 32 - (1+8+19) = 4 bits |
| Register Code Part | Number of registers | $\log_2(\text{Number of registers})$ | 256 registers $\implies \log_2(256) = 8$ bits |
| Address Part | Memory size (number of words) | $\log_2(\text{Memory size in words})$ | 512K words = $2^{19}$ words $\implies 19$ bits |
Additional Information: Memory Addressing and Instruction Set Architecture
Computer memory is organized as a sequence of locations, each with a unique address. The address part of an instruction tells the computer which memory location to access for data or the next instruction. The number of bits in the address part directly determines the maximum amount of memory that can be addressed.
The operation code (opcode) specifies the operation to be performed by the instruction (e.g., add, subtract, load, store). The number of bits in the opcode determines the total number of unique operations (instructions) the computer can perform.
Registers are small, high-speed storage locations within the CPU. The register code part identifies which specific register is to be used in the operation.
Addressing modes define how the operand (the data the instruction operates on) is located. Common modes include direct addressing (the address part contains the actual memory address) and indirect addressing (the address part contains the address of a memory location that holds the actual address of the operand).
Understanding how these parts fit together is key to understanding the Instruction Set Architecture (ISA) of a computer.
Important Questions from Instruction Format - Teaching
The following program is stored in the memory unit of the basic computer. Give the content of accumulator register in hexadecimal after the execution of the program.
Location
Instruction
010
CLA
011
ADD 016
012
BUN 014
013
HLT
014
AND 017
015
BUN 013
016
C1A5
017
93C6
A micro instruction format has micro operation field which is divided into 2 subfields F1 and F2, each having 15 distinct microoperations, condition field CD for four status bits, branch field BR having four options used in conjunction with address field AD. The address space is of 128 memory words. The size of micro instruction is:
Which of the following is not an example of pseudo‐instruction?
A Computer uses a memory unit with 256K word of 32 bits each. A binary instruction code is stored in one word of memory. The instruction has four parts: an indirect bit, an operation code and a register code part to specify one of 64 registers and an address part. How many bits are there in operation code, the register code part and the address part?
