Understanding Microprocessor Interrupts

An interrupt is a signal sent to the processor indicating an event that needs immediate attention. When an interrupt occurs, the processor stops its current task, saves its state, and executes a special routine called an Interrupt Service Routine (ISR) to handle the event. After the ISR completes, the processor resumes its original task.

Vectored vs. Non-Vectored Interrupts

Interrupts can be categorized based on how the processor finds the ISR:

• Vectored Interrupts: In this system, the interrupting device provides a unique piece of information (a vector) directly to the processor. This vector is used to calculate or directly identify the memory address of the specific ISR for that device. The processor knows exactly where to go without needing to search.
• Non-Vectored Interrupts: In this system, all interrupts signal the processor through a single interrupt request line. When an interrupt occurs, the processor typically needs to poll (check) the connected devices sequentially to determine which device triggered the interrupt. Once identified, the processor can then find the corresponding ISR, perhaps through a lookup table or by executing a specific instruction provided by the device.

Analysis of Interrupt Options

Let's examine the characteristics of the given interrupt types, commonly found in microprocessors like the Intel 8085:

TRAP Interrupt

TRAP is a special type of hardware interrupt. It is non-maskable (meaning it cannot be disabled by software) and is considered vectored. It has a fixed interrupt vector address at memory location 0024H.

INTR Interrupt

INTR is a maskable hardware interrupt request line. When the INTR line is activated, the processor acknowledges it. However, the interrupting device must then place a specific instruction (like a Restart or CALL instruction) onto the data bus. This instruction tells the processor where to find the ISR. Since the INTR signal itself does not directly provide a fixed vector address and relies on external hardware to supply the vectoring information (via an instruction), it is generally classified as a non-vectored interrupt in contrast to interrupts with pre-defined hardware vectors.

RST 7.5 Interrupt

RST 7.5 is another hardware interrupt. It is maskable and vectored. It has a fixed interrupt vector address at memory location 003CH. It is also unique because it is edge-triggered, meaning it responds to a rising edge on the RST 7.5 line, even if it's masked.

RST 3 Interrupt

RST 3 refers to the Restart instruction (RST 3) which is often used to handle interrupts. In systems like the 8085, interrupts can be configured to trigger specific RST instructions (RST 0 through RST 7). Each RST instruction corresponds to a specific, fixed memory address (e.g., RST 3 corresponds to vector address 0018H). Therefore, interrupts handled via RST instructions are considered vectored because the processor is directed to a specific ISR location based on the RST instruction provided.

Summary Table

Here's a comparison of the interrupt types:

Based on this analysis, the INTR interrupt is the one that does not inherently provide a fixed vector address to the processor and relies on external hardware for vectoring, making it the non-vectored interrupt among the choices.