Interrupt Selection for Object Counting

The task is to count sequential objects crossing a window using an 8085 microprocessor interrupt. Key parameters are: object presence duration ($100 ms$ to $2 s$), processor interrupt handling time ($1 ms$), and the need for error-free counting amidst variable speeds.

Understanding 8085 Interrupt Types

The 8085 has maskable hardware interrupts (RST 5.5, RST 6.5, RST 7.5) and a general-purpose interrupt request (INTR).

• Level-Triggered Interrupts (RST 5.5, RST 6.5): These interrupts remain active as long as the interrupt line is asserted (high). They are less suitable for counting distinct, sequential events if the processor is busy, as they might miss intermediate events if the line stays high.
• Edge-Triggered Interrupts (RST 7.5): RST 7.5 is edge-triggered (positive edge) and features an internal flip-flop to latch the interrupt request. This makes it effective at detecting the start of each event, even if the processor is busy. It's a strong candidate for sequential event counting.
• General-Purpose Interrupt (INTR): INTR is also typically used with external edge-detection circuitry. It is highly flexible, requiring external hardware to acknowledge the interrupt and provide the specific instruction (like RST or CALL) to the processor.

Choosing the Best Interrupt for Error-Free Counting

For error-free counting of sequential objects with varying speeds and durations, edge-triggered interrupts are preferred over level-triggered ones. This ensures each distinct object arrival is initially detected.

Comparing RST 7.5 and INTR:

• RST 7.5's internal latching reliably captures the start of each object's passage, making it suitable for many sequential counting tasks.
• However, the INTR pin offers the maximum flexibility. For guaranteed error-free counting under potentially challenging conditions (e.g., extremely rapid succession of objects, or complex timing interactions between object duration and processor load), custom external hardware connected to INTR can be designed. This hardware can implement sophisticated request buffering, unique instruction generation for each event, or precise timing logic that ensures no object is missed. This adaptability makes INTR the superior choice when absolute error-free counting is paramount and needs to accommodate the most demanding scenarios.

Therefore, INTR provides the necessary flexibility for robust, error-free object counting.