Assertion (A) : Information is transferred from STM to LTM.
Reason (R) : Information maintained in the rehearsal buffer is prevented from decaying in STM.
The question includes two statements: an Assertion (A) and a Reason (R). We need to evaluate these statements to determine their validity and the relationship between them.
Although both statements are true, the reason provided (R) is not the direct explanation for the assertion (A). The assertion describes the process of transferring information to LTM, while the reason explains a method of maintaining information in STM. Therefore, the correct answer is that both statements are true, but (R) is not the correct explanation of (A).
Which among the following is incorrect about cache memory?
Which among the following statements is incorrect about secondary memory?
Which among the following registers in Instruction Cycle holds the last instruction fetched?