Analyzing 60-Degree PWM Inverter Characteristics

A 60-degree PWM inverter power supply is a type of voltage source inverter that uses Pulse Width Modulation (PWM) techniques with specific gating patterns to control the output voltage and frequency. The term "60-degree PWM" often refers to particular modulation strategies or characteristics of the resulting voltage waveform or switch operation.

Let's analyze each statement provided regarding the 60-degree PWM inverter power supply:

• Statement A: Power devices are made 'ON' for 1/3 of the cycle.

  1/3 of a cycle (360 degrees) is 120 degrees. This statement claims each power device is ON for a total of 120 degrees per fundamental cycle. While 120-degree conduction is a mode for inverters, standard PWM techniques involve switching within the conduction period, resulting in cumulative ON time based on the modulation index. If this statement refers to the cumulative ON time from the gate signal, it means the switch is ON for 120 degrees and OFF for 240 degrees. Let's evaluate other statements based on the provided correct option.

• Statement B: Power devices are made 'OFF' for 1/3 of the cycle.

  This statement claims each power device is OFF for a total of 120 degrees per fundamental cycle. This implies the device is ON for the remaining 240 degrees. Based on the provided correct answer, this statement is considered true for this specific "60-degree PWM" operation. This suggests a particular gating strategy where the cumulative duration each switch is turned OFF by its gate signal is 120 degrees per cycle.

• Statement C: The phase voltage = 0.57735 V supply.

  The value 0.57735 is approximately \( \frac{1}{\sqrt{3}} \). If \( V_{supply} \) refers to the DC link voltage (\( V_{dc} \)), this statement suggests that the phase voltage magnitude is approximately \( \frac{1}{\sqrt{3}} V_{dc} \). This value is significant in inverter control. In Space Vector PWM (SVPWM) at maximum modulation index, the peak value of the fundamental phase voltage component is \( \frac{V_{dc}}{\sqrt{3}} \). The RMS value would be \( \frac{V_{dc}}{\sqrt{3}\sqrt{2}} = \frac{V_{dc}}{\sqrt{6}} \approx 0.408 V_{dc} \). However, if Statement C refers to the peak phase voltage being \( \frac{V_{dc}}{\sqrt{3}} \), then it is consistent with maximum voltage operation in SVPWM. Given that Statement E is correct (Line voltage < V supply), which is true for \( V_{LL,RMS} = \frac{V_{dc}}{\sqrt{2}} \) (from \( V_{ph,peak} = V_{dc}/\sqrt{3} \)), Statement C is likely referring to the peak phase voltage being \( \approx \frac{V_{dc}}{\sqrt{3}} \) or some characteristic value related to this factor, with \( V_{supply} \) being \( V_{dc} \).

• Statement D: Line voltage = V supply.

  If \( V_{supply} \) is the DC link voltage \( V_{dc} \), this statement claims the output line voltage equals the DC supply voltage. As discussed in Statement C and E, the output fundamental RMS line voltage from a typical PWM inverter is generally less than or equal to \( V_{dc} \), and often less than \( V_{dc} \) depending on the modulation index. Therefore, this statement is likely incorrect.

• Statement E: Line voltage < V supply.

  Assuming \( V_{supply} \) is the DC link voltage \( V_{dc} \), this statement claims the output line voltage is less than the DC supply voltage. This is generally true for the fundamental RMS line voltage in PWM inverters operating at typical modulation indices, including maximum voltage operation in common schemes like SVPWM where \( V_{LL,RMS} = \frac{V_{dc}}{\sqrt{2}} \approx 0.707 V_{dc} \). Therefore, this statement is considered correct.

Based on the analysis and the provided correct option, statements B, C, and E are correct.

Statement B indicates a specific gating pattern where power devices are turned OFF for 1/3 of the cycle. Statement C suggests a relationship between the phase voltage magnitude and the supply voltage, consistent with maximum voltage capability in certain advanced PWM techniques. Statement E confirms that the resulting line voltage magnitude is below the DC supply voltage, which is typical for voltage source inverters.

Statements A and D contradict the correct statements and typical inverter operation characteristics or voltage relationships.

Therefore, the correct statements are B, C, and E.

Revision Table: 60‐Degree PWM Inverter Facts

Additional Information on PWM Inverters

Pulse Width Modulation (PWM) in inverters is used to control the magnitude and frequency of the output voltage while minimizing harmonics. Different PWM strategies exist, such as:

• Sinusoidal PWM (SPWM): A sinusoidal reference wave is compared with a high-frequency triangular carrier wave. The intersection points determine the switching times.
• Space Vector PWM (SVPWM): This method uses space vector representation of voltages and aims to maximize the output voltage and reduce harmonics compared to SPWM. SVPWM can achieve up to 15% higher voltage utilization than SPWM.
• Discontinuous PWM (DPWM): In DPWM, the modulating signal for one or more phases is clamped to the positive or negative DC rail voltage for a certain duration (e.g., 60 degrees per half cycle). This reduces switching losses in the clamped phase legs. "60-degree PWM" might refer to a type of DPWM where the clamping period is 60 degrees per half cycle. However, during clamping, the switches in that leg are typically continuously ON (not OFF) for that period.

The relationship between DC link voltage (\( V_{dc} \)), fundamental RMS phase voltage (\( V_{ph1,RMS} \)), and fundamental RMS line voltage (\( V_{LL1,RMS} \)) depends on the modulation strategy and index:

• In a 3-phase system, \( V_{LL1,RMS} = \sqrt{3} V_{ph1,RMS} \) for star-connected loads.
• For 180-degree conduction, \( V_{ph1,RMS} = \frac{\sqrt{2}}{\pi} V_{dc} \) and \( V_{LL1,RMS} = \frac{\sqrt{6}}{\pi} V_{dc} \approx 0.78 V_{dc} \).
• For SVPWM operating at maximum modulation index, the peak line voltage equals \( V_{dc} \), leading to \( V_{LL1,peak} = V_{dc} \) and \( V_{LL1,RMS} = \frac{V_{dc}}{\sqrt{2}} \approx 0.707 V_{dc} \). The corresponding peak phase voltage is \( V_{ph1,peak} = \frac{V_{dc}}{\sqrt{3}} \approx 0.57735 V_{dc} \). The RMS phase voltage is \( V_{ph1,RMS} = \frac{V_{dc}}{\sqrt{6}} \approx 0.408 V_{dc} \).

Statement C likely relates to the peak phase voltage achievable, aligning with SVPWM characteristics. Statement E reflects that the output fundamental line voltage magnitude is controlled and is typically less than the DC source voltage in practical operation.