Understanding Static RAM (SRAM) Cell Composition

Static Random-Access Memory (SRAM) is a type of random-access memory that uses latching circuitry to store each bit. Unlike Dynamic RAM (DRAM), SRAM does not need to be periodically refreshed to maintain the data.

What Makes Up an SRAM Cell?

The fundamental building block of an SRAM is the memory cell. This cell is designed to store a single bit of binary data (either a 0 or a 1). The key to SRAM's 'static' nature is the use of a flip-flop or latch circuit, which holds its state as long as power is supplied.

While the most common type of CMOS SRAM cell today uses six transistors (a "6T cell"), which includes two cross-coupled inverters (4 transistors) and two access transistors, other configurations exist, especially in older technologies or simplified models focusing just on the core storage element.

The question asks about the composition of an SRAM cell. Let's look at the options in the context of how a binary value can be stored using transistors.

• Options with Capacitors: Options 2 and 4 mention capacitors. Capacitors are the primary storage elements in Dynamic RAM (DRAM). DRAM stores data as a charge on a capacitor, which leaks over time, requiring periodic refreshing. Static RAM, by definition, uses a latch and does not need this refreshing process. Therefore, options including capacitors are incorrect for a Static RAM cell.
• Option with 2 MOS Transistors: A single transistor cannot form a stable latch that can hold two states (0 and 1). A minimum of two cross-coupled elements is typically needed for a basic latch. While some complex single-transistor or two-transistor dynamic structures exist, a static cell requires more for stable, latching storage. Thus, 2 MOS transistors are generally insufficient for a standard SRAM storage cell.
• Option with 4 MOS Transistors: A configuration using 4 MOS transistors can form a basic storage latch. For example, in older NMOS technology, a cell could consist of two cross-coupled NMOS transistors with depletion-mode NMOS transistors acting as loads. The two cross-coupled switching transistors and their two load transistors total 4 transistors forming the core latch. Another interpretation is that the core flip-flop structure itself requires 4 transistors (e.g., two cross-coupled CMOS inverters using only the switching transistors, excluding the load transistors, though this is less standard) or focusing on the minimal number required for a basic latching action. Given the options and the provided correct answer, "4 MOS transistors" most likely refers to a valid, albeit perhaps not the most common modern, configuration capable of static data storage or the core latch part.

Based on the typical structures used for Static RAM storage and evaluating the given options, a configuration built with 4 MOS transistors is capable of forming the core latching mechanism required for static data storage, distinguishing it from DRAM (which uses capacitors).

Therefore, among the provided options, the structure that correctly represents a configuration suitable for a Static RAM cell is one containing 4 MOS transistors.

Revision Table: Key SRAM Concepts

Additional Information: SRAM vs. DRAM Cell Structure

It is crucial to understand the fundamental difference in how SRAM and DRAM cells store data:

• SRAM Cell: Relies on a latch (typically formed by cross-coupled inverters) to store data. This means it will hold its state indefinitely as long as power is supplied, without the need for constant refreshing. The number of transistors can vary (4T, 6T, 8T), but the core is a latch. The 6T CMOS cell is the most common today due to its low power consumption and speed, consisting of two CMOS inverters (4 transistors) and two access transistors (2 transistors). However, older or specific designs might use 4 transistors for the core storage element.
• DRAM Cell: Stores data as electrical charge on a capacitor. A single transistor (usually an NMOS transistor) acts as an access switch to connect the capacitor to a bit line for reading or writing. Because the charge on the capacitor leaks away over time, the data must be periodically read and rewritten (refreshed). This structure is simpler (1T1C - 1 transistor, 1 capacitor) and allows for higher density memory compared to SRAM.

The presence of capacitors in a memory cell is characteristic of DRAM, not SRAM. The latching structure built with transistors is characteristic of SRAM.