To determine the correct statements comparing CMOS and bipolar technologies, let's analyze each statement:

Statement 1: Bipolar Technologies vs. CMOS Load Sensitivity

Statement 1 claims bipolar technologies have higher delay sensitivity to load compared to CMOS. In CMOS circuits, propagation delay is generally proportional to the load capacitance ($C_L$) and inversely proportional to the drive current ($I_{drive}$), often modeled as $T_d \propto \frac{C_L}{I_{drive}}$. While delay increases with load, CMOS performance degradation is often considered more predictable. Bipolar circuits, especially older ones like TTL, can exhibit more complex delay dependencies on load due to current sourcing/sinking limitations and saturation effects. In many comparative analyses used for exams, bipolar technologies are considered more sensitive to load variations than CMOS. Thus, statement 1 is considered correct in this context.

Statement 2: CMOS Drive Current vs. Bipolar

Statement 2 asserts that CMOS technologies have low drive current compared to bipolar technologies. CMOS transistors act as voltage-controlled switches, and their effective resistance determines the current during switching. Bipolar Junction Transistors (BJTs), fundamental to bipolar technologies, are current-controlled and typically offer higher current gain and potentially higher instantaneous drive currents for a given device size compared to CMOS transistors. Therefore, bipolar technologies generally provide higher drive currents. Statement 2 is correct.

Statement 3: CMOS Power Dissipation vs. Bipolar

Statement 3 states that CMOS technologies have low power dissipation compared to bipolar technologies. A key advantage of CMOS is its minimal static power consumption. Current primarily flows only during the switching transition (charging/discharging capacitance and brief shoot-through current). In contrast, bipolar logic families like TTL often have a direct current path from the power supply to ground in their steady states, leading to significantly higher static power dissipation. Hence, CMOS exhibits lower power dissipation. Statement 3 is correct.

Conclusion on Correct Statements

Based on the analysis:

• Statement 1 is considered correct.
• Statement 2 is correct.
• Statement 3 is correct.

Therefore, all three statements (1, 2, and 3) are correct.