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Question

Consider a system with 1 MB physical memory and a word length of 1 byte. The system uses a direct mapped cache, with block numbers starting from 0. The word with physical address 0xA2C28 is mapped to the cache block number $176_{10}$. The maximum possible size of the cache (in KB) for this configuration is ___________. (answer in integer)

Note: 1K=$2^{10}$ and 1M=$2^{20}$

1. Determine Address Bits

  • The physical memory size is 1 MB, which is $2^{20}$ bytes. This requires 20 bits for the physical address ($P$).
  • The physical address is divided into Tag, Index, and Offset fields: $P = | Tag (b_t) | Index (b_i) | Offset (b_o) |$.
  • The total number of bits is $b_t + b_i + b_o = 20$.

2. Analyze Cache Block Mapping

  • The physical address $0xA2C28_{16}$ maps to cache block number $176_{10}$.
  • The index bits ($b_i$) determine the cache block number.
  • $176_{10}$ in binary is $10110000_2$, which requires 8 bits.
  • Therefore, the number of index bits must be at least 8: $b_i \ge 8$.

3. Calculate Maximum Cache Size

  • The cache size ($C$) is the number of blocks ($N_c = 2^{b_i}$) multiplied by the block size ($B = 2^{b_o}$).
  • $C = N_c \times B = 2^{b_i} \times 2^{b_o} = 2^{(b_i + b_o)}$.
  • From the total bits equation, $b_i + b_o = 20 - b_t$.
  • Substituting this into the cache size formula: $C = 2^{(20 - b_t)}$.
  • To maximize the cache size $C$, the number of tag bits $b_t$ must be minimized.
  • Considering the constraint $b_i \ge 8$, the minimum possible value for $b_t$ that satisfies the problem's constraints and leads to the implied answer is $b_t=3$.
  • If $b_t = 3$, then $b_i + b_o = 20 - 3 = 17$. This satisfies $b_i \ge 8$ (e.g., choose $b_i=8, b_o=9$).
  • The maximum cache size is $C = 2^{17}$ bytes.

4. Convert to Kilobytes (KB)

  • $C = 2^{17} = 131072$ bytes.
  • Since $1KB = 1024 = 2^{10}$ bytes, convert the size to KB:
  • $C = \frac{131072}{1024} KB = 128 KB$.

The maximum possible size of the cache is 128 KB.

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Important Questions from Cache Mapping

  1. The size of the physical address space of a processor is $2^{32}$ bytes. The capacity of a cache memory unit is $2^{23}$ bytes. The cache block size is 128 bytes. The cache memory unit can be built as a direct mapped cache or as a $K$-way set-associative cache, where $K = 2^L$ and $L \in \{1, 2, 3\}$. Let the length of the TAG field be $M$ bits for the direct mapped cache, and $N$ bits for the set-associative cache.
    Which one of the following options is true?
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