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Question

Assume that the 8255 gets selected whenever A15 - A11 are high during I/O read or write cycles. The A2 and A1 are connected to A1 and A0 of 8255 chip, then the address for port C of 8255 is
(a) FEh
(b) 03h
(c) FF03h
(d) FFh
Codes :

The correct answer is
(c) and (d) are correct

The question asks us to determine the address for port C of the 8255 Programmable Peripheral Interface (PPI) chip, based on certain address lines. Here is the step-by-step explanation:

Understanding the addressing method:

The question states that the 8255 is selected when address lines A15 to A11 are high. This means that the upper bits of the address bus are set to binary 11111. Hence, the higher nibble of the address would be 1111 1000 (indicating some part of the address space).

Connection of A2 and A1:

A2 and A1 are connected to A1 and A0 of the 8255. This means the last two bits of the address bus (A1 and A0) will determine which port or control word of 8255 is accessed.

8255 Port Addressing:

Address BitsPort/Register
00 (i.e., A1=0, A0=0)Port A
01 (i.e., A1=0, A0=1)Port B
10 (i.e., A1=1, A0=0)Port C
11 (i.e., A1=1, A0=1)Control Register

For Port C, A1 must be 1 and A0 must be 0.

Address Calculation:

Given A15 - A11 are high (i.e., 1111 1... .... ....). The exact required bits for Port C will be:

1111 1XXX XXXX XX10, replacing X with any combination of 0 or 1.

The choice that matches this condition is pattern FF03h. FF03 in binary is 1111 1111 0000 0011, aligning perfectly with 1111 1000 (leading bits) and XX10 (end bits for Port C).

Verifying the options:

  • (a) FEh: Incorrect, as this uses only 8 bits.
  • (b) 03h: Incorrect, as this is just the lower part and doesn't meet the condition for higher A15 - A11 bits.
  • (c) FF03h: Correct, as it satisfies both higher and lower bit conditions.
  • (d) FFh: Also matches the higher 8 bits pattern for I/O cycle, so it remains compatible but usually impractical without lower bits context.

Conclusion:

The correct choices are (c) FF03h and (d) FFh, which follow the setup for the I/O addressing as described.

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