Note: 1G=$10^9$
Pipelined vs Non-Pipelined Performance Calculation
The problem asks for the speed-up obtained by a pipelined design compared to a non-pipelined design, considering different clock rates, cycles per instruction (CPI), and pipeline stalls.
Non-Pipelined Execution Analysis
First, calculate the execution characteristics of the non-pipelined unit.
- Clock Rate ($R_{NP}$): 1.6 GHz = $1.6 \times 10^9$ Hz
- Average Cycles Per Instruction ($CPI_{NP}$): 5 cycles/instruction
The execution time for a program with N instructions on the non-pipelined unit can be represented as:
$ T_{NP} = \frac{N \times CPI_{NP}}{R_{NP}} = \frac{N \times 5}{1.6 \times 10^9} \text{ seconds} $
Pipelined Execution Analysis
Next, analyze the pipelined unit. The goal is 1 instruction per clock cycle, but practical limitations exist.
- Clock Rate ($R_{P}$): 1.2 GHz = $1.2 \times 10^9$ Hz
- Ideal CPI (goal): 1 cycle/instruction
- Stall Condition: 30% of instructions stall for 2 cycles.
Calculate the actual average CPI for the pipelined design:
Stall cycles per instruction = (Percentage of stalled instructions) $\times$ (Stall cycles per stalled instruction)
$ \text{Stall cycles per instruction} = 0.30 \times 2 = 0.6 \text{ cycles/instruction} $
Actual Average CPI ($CPI_{P}$) = Ideal CPI + Stall cycles per instruction
$ CPI_{P} = 1 + 0.6 = 1.6 \text{ cycles/instruction} $
The execution time for the same program with N instructions on the pipelined unit is:
$ T_{P} = \frac{N \times CPI_{P}}{R_{P}} = \frac{N \times 1.6}{1.2 \times 10^9} \text{ seconds} $
Speed-up Calculation
Speed-up is defined as the ratio of the execution time of the non-pipelined design to the execution time of the pipelined design.
$ \text{Speed-up} = \frac{T_{NP}}{T_{P}} $
Substitute the expressions for $T_{NP}$ and $T_{P}$:
$ \text{Speed-up} = \frac{\frac{N \times 5}{1.6 \times 10^9}}{\frac{N \times 1.6}{1.2 \times 10^9}} $
The number of instructions (N) and the base factor $10^9$ cancel out:
$ \text{Speed-up} = \frac{5 / 1.6}{1.6 / 1.2} = \frac{5}{1.6} \times \frac{1.2}{1.6} $
$ \text{Speed-up} = \frac{5 \times 1.2}{1.6 \times 1.6} = \frac{6}{2.56} $
$ \text{Speed-up} \approx 2.34375 $
Rounding the speed-up to two decimal places gives 2.34.
Important Questions from Instruction Pipelining
- The right sequence of suboperations that are performed in arithmetic pipeline is-
A. Align the mantissas
B. Add or subtract the mantissas
C. Normalize the result
D. Compare the exponents
Choose the correct answer from the options given below: - A 5-stage instruction pipeline has stage delays of 180, 250, 150, 170, and 250, respectively, in nanoseconds. The delay of an inter-stage latch is 10 nanoseconds. Assume that there are no pipeline stalls due to branches and other hazards. The time taken to process 1000 instructions in microseconds is ____________ (rounded off to two decimal places)
- Which one of the following is a technique of decomposing a sequential process into sub-operations, with each sub-process being executed in a special dedicated segment that operates concurrently with all other segments?
- The EX stage of a pipelined processor performs the memory read operations for LOAD instructions, and the operations for the arithmetic and logic instructions. Let $t_{EX}$ denote the time taken by the EX stage to perform the operation for an instruction. For each instruction type, the values of $t_{EX}$ and $M$ (the number of instructions of that type in a sequence of 100 instructions for a program P), are given in the table below.
The duration of the pipeline clock cycle is 1 nanosecond. Assume that the latch time for the interstage buffers in the pipeline is negligible.Instruction $t_{EX}$ in nanoseconds $M$ LOAD 1.8 15 IMUL 1.5 10 IDIV 2.5 5 FADD 1.7 10 FSUB 1.7 5 FMUL 2.8 15 FDIV 3.2 5 All other instructions Less than 1.0 35
When program P is executed, the number of clock cycles for which the pipeline is stalled due to structural hazards in the EX stage is ______. (answer in integer) - Pipelining improves performance by :
